Chip Seek Industry Analysis

Packaging the AI Scale-Up: CoWoS-L, EMIB-T and the Race to Fit More HBM

The next bottleneck in AI computing may not be the transistor. It may be the package that must connect more compute, more HBM, more power and more bandwidth in a physically limited area.

Published by Chip Seek | Semiconductor packaging, AI infrastructure and supply-chain research

Executive summary

AI accelerators are becoming larger, more heterogeneous and more dependent on high-bandwidth memory. That combination is pushing advanced packaging away from a supporting role and into the center of semiconductor product strategy.

Traditional 2.5D designs based on a silicon interposer remain highly effective, but the physical size of the interposer, reticle exposure constraints, manufacturing cost and available capacity are becoming increasingly important. TSMC's CoWoS-L addresses this pressure by combining a redistribution-layer-based interposer with embedded silicon bridges, allowing designers to connect larger and more complex combinations of compute dies and HBM.

Intel's EMIB-T represents a different path. Instead of relying on one very large silicon interposer, it uses embedded bridge technology and through-silicon vias to shorten signal paths and improve package-level connectivity. The architecture may offer a useful alternative where cost, capacity, package size or customer-specific integration requirements make a full CoWoS-L solution less attractive.

Our view: CoWoS-L is likely to remain the leading solution for the most demanding AI packages through 2028, while EMIB-T and other bridge-based architectures capture selected ASIC, accelerator and overflow opportunities.

1. AI performance is now a packaging problem

The AI semiconductor race is often described through process nodes, accelerator architectures and model performance. Those factors remain important, but they do not tell the entire story. A high-performance AI device is a system made up of compute dies, cache, memory interfaces, HBM stacks, power delivery, thermal structures and a substrate that must keep all of these elements electrically and mechanically stable.

Every generation of AI infrastructure increases pressure on that system. Larger models require more memory capacity and bandwidth. Training and inference workloads demand more parallel compute. Hyperscale data centers want higher performance per rack, but they also need predictable power consumption, thermal behavior and serviceability. The result is a move toward increasingly integrated packages and rack-scale systems.

This trend changes the meaning of a semiconductor bottleneck. Even if a compute die can be manufactured successfully, the product may still be limited by the ability to place enough memory around it, route thousands of high-speed connections, control warpage, remove heat and achieve acceptable assembly yield.

The package must solve five problems at once

Bandwidth: connect compute dies and HBM with short, dense and reliable paths.
Area: fit more chiplets and memory stacks without exceeding manufacturing limits.
Power: deliver high current while controlling voltage drop and electrical noise.
Thermals: remove heat from a dense package operating under sustained workloads.
Yield: maintain commercially acceptable output as the package becomes larger and more complex.

2. The reticle boundary is becoming a strategic boundary

At the wafer level, lithography equipment exposes patterns through a reticle. The exposure field places a practical limit on how large a single structure can be created in one step. Advanced packaging does not eliminate this limitation. Instead, it gives system designers different ways to assemble multiple pieces of silicon into a larger functional unit.

For earlier generations of AI accelerators, a silicon interposer could connect a relatively manageable number of compute dies and HBM stacks. As package dimensions grow, however, a larger interposer can increase manufacturing complexity, mask and exposure constraints, defect sensitivity, material cost and warpage risk.

The important shift is that “larger” does not simply mean adding more silicon. The package must also preserve signal integrity across high-speed interfaces. It must support microbumps and fine routing, keep thermal expansion under control, and survive assembly, test and field operation. This is why the industry is exploring multiple paths rather than waiting for one universal package.

The competitive question is no longer only “Which chip is fastest?” It is also “Which packaging architecture can scale the whole system without destroying yield or economics?”

3. CoWoS-S and CoWoS-L: related technologies, different scaling roles

TSMC's CoWoS family has become one of the most visible foundations of high-performance computing and AI packaging. CoWoS-S uses a silicon interposer to connect compute dies and HBM. It offers high-density interconnects and a mature production ecosystem, which makes it suitable for many current designs.

CoWoS-L extends the concept for larger and more complex packages. Rather than depending entirely on one large silicon interposer, it combines an RDL-based interposer with embedded local silicon interconnects or silicon bridges. This creates more flexibility in how compute dies and HBM are connected, particularly when a design must move beyond the practical scaling range of conventional interposer layouts.

Dimension	CoWoS-S	CoWoS-L
Core structure	Large silicon interposer	RDL-based interposer with embedded silicon bridges
Best-known strength	Mature high-density integration	More flexible scaling for larger compute and HBM combinations
Typical pressure point	Interposer area and reticle-related limits	Higher package complexity, cost and capacity requirements
Strategic role	Important for established and moderately scaled designs	Leading candidate for the next wave of large AI packages

The two solutions should not be treated as simple substitutes. Package selection depends on die size, HBM count, bandwidth, power, substrate design, thermal architecture, customer qualification and the availability of manufacturing capacity.

4. Why HBM changes the economics of packaging

HBM is not simply a memory component placed next to a processor. Its value depends on the quality of the entire connection between the HBM stacks and the compute dies. The package must support a very wide interface with extremely short electrical paths, while preserving signal integrity and thermal performance.

As AI accelerators add more HBM modules, the package grows in at least three directions: physical area, routing complexity and thermal load. Additional memory may raise system performance, but it also consumes package space and increases the number of interconnects that must be assembled and tested.

This produces a difficult trade-off. A package with fewer HBM stacks may be cheaper and easier to manufacture, but may not provide enough bandwidth. A much larger package can deliver exceptional performance, but its cost and defect sensitivity rise. For AI system builders, the best design is therefore not necessarily the one with the highest theoretical memory bandwidth. It is the one that provides a reliable balance between performance, yield, power and total cost of ownership.

Supply-chain implication: HBM availability and advanced packaging capacity are increasingly linked. A customer may secure GPU or ASIC wafers but still face a shipment constraint if HBM integration, interposer production, substrate supply or advanced test capacity cannot keep pace.

5. Demand is expanding from GPUs to custom AI ASICs

The packaging market is being shaped by two overlapping demand streams. The first is the continued expansion of merchant AI accelerators. The second is the growing number of custom chips designed by hyperscale cloud providers.

TrendForce expects NVIDIA's high-end GPU shipments to grow strongly in 2026 as the company promotes integrated rack-scale solutions with high chip content. AMD is also pushing its next generation of AI accelerators, including the MI400 and MI450 families, from the second half of 2026.

Custom silicon adds another layer of complexity. Google is expected to remain one of the strongest CSP ASIC drivers, with TPU v7 as a major product family. AWS is moving toward Trainium v3 and continues to develop its own AI server platform. Microsoft and Meta remain heavily associated with GPU-based infrastructure, but both are also evaluating and deploying purpose-built silicon for selected workloads.

These customers do not all need the same package. A training accelerator, an inference chip and a networking or memory controller may have very different requirements. This diversity is good for advanced packaging suppliers because it increases the number of possible designs, but it also makes qualification and capacity planning more difficult.

Demand source	Packaging pressure	What to monitor
High-end GPU platforms	More compute and HBM per package	Shipment growth, rack architecture and HBM allocation
Cloud-provider ASICs	Customer-specific package and qualification flows	Tape-outs, production ramps and design reuse
Inference platforms	Performance-per-watt and cost sensitivity	Workload mix, edge deployment and total system cost

6. Why CoWoS-L is likely to remain the mainstream option through 2028

CoWoS-L is receiving attention not because it removes every packaging challenge, but because it offers a practical bridge between today's mature 2.5D ecosystem and tomorrow's larger AI systems.

First, it builds on a proven manufacturing environment. Product teams prefer to extend a qualified technology platform rather than restart the entire package-development process. Existing design know-how, equipment, materials, assembly experience and customer relationships can reduce execution risk.

Second, it provides a path to larger integration. Embedded silicon bridges can support dense local connections without requiring the entire package to be one continuous silicon interposer. That flexibility matters when a design must combine multiple compute chiplets, HBM stacks and heterogeneous functions.

Third, yield matters as much as peak performance. A very ambitious architecture is not commercially useful if its defect rate, rework rate or qualification time makes volume production unpredictable. CoWoS-L's expected advantage is therefore not only technical capability, but also the confidence created by process maturity and accumulated production learning.

Fourth, the ecosystem is already forming around it. Current AI accelerator programs, HBM suppliers, substrate makers, assembly houses and system companies are aligning their roadmaps around advanced 2.5D integration. This ecosystem effect can reinforce the leading architecture even when alternatives look attractive on paper.

This does not mean CoWoS-L will win every design. It means the default choice for the most demanding AI packages is likely to remain the platform with the strongest combination of performance, yield, capacity and customer confidence.

7. EMIB-T: a credible alternative, not just a backup plan

Intel's EMIB approach embeds a silicon bridge in the package substrate rather than using one very large silicon interposer for the entire package. EMIB-T adds through-silicon vias to the bridge architecture, helping shorten signal paths and improve connectivity for demanding multi-die systems.

The appeal is clear. A bridge-based architecture may reduce the amount of expensive large-area interposer material and can offer a different manufacturing flow. It may be especially useful for customer-specific ASICs, selected AI accelerators and programs that need an alternative source of advanced packaging capacity.

However, EMIB-T also has trade-offs. Package-level performance depends on substrate routing density, line-and-space capability, microbump design, bridge placement, thermal behavior and the maturity of the complete assembly flow. A lower interposer requirement does not automatically mean lower total package cost, because the design may shift cost and complexity into substrates, bridges, TSVs, assembly and test.

TrendForce has identified Google as a possible EMIB-T adopter from 2027 and reported that AWS is testing EMIB-based solutions. These developments should be interpreted as evidence of customer diversification rather than proof that the industry is moving away from CoWoS-L altogether.

Potential advantage
Less dependence on one very large silicon interposer and a differentiated scaling path.

Key challenge
Substrate routing density, bridge integration, TSV process maturity and qualification.

Likely role
Selected ASIC and accelerator programs, plus capacity diversification and overflow.

8. The real competition is about capacity, yield and time-to-volume

Technology comparisons often focus on interposer size or theoretical bandwidth. For buyers and system companies, the more important question is whether a package can enter volume production on schedule and at a predictable cost.

Large AI packages are sensitive to defects. As the package area rises, the opportunity for a defect somewhere in the assembly can also rise. At the same time, more HBM stacks, more microbumps and more routing layers create additional inspection and test requirements. Warpage and thermal-mechanical stress can affect both yield and long-term reliability.

Capacity planning therefore has to cover more than wafer fabrication. It includes interposer and RDL capability, bridge or TSV production, substrates, microbumps, assembly tools, thermal interfaces, final test and burn-in. A shortage in any one of these steps can hold back the complete AI product.

Capacity: How many packages can be produced at the required size and configuration?
Yield: How does output change as package area, HBM count and chiplet count increase?
Qualification: How quickly can a new package pass electrical, thermal, mechanical and reliability tests?
Cost: What is the full package cost after assembly, test, scrap, rework and inventory buffers?
Flexibility: Can the package support multiple die versions or customer configurations?

The strongest packaging platform will be the one that converts technical ambition into repeatable, high-volume output.

9. What this means for the semiconductor supply chain

The transition to larger AI packages expands the value chain. Demand is not limited to GPU and ASIC wafers. It reaches every supplier that helps build, connect, protect, test or cool the package.

Memory

HBM capacity, stack generation, thermal behavior and allocation will influence accelerator shipment timing.

Substrates

Fine line-and-space routing, warpage control and large package formats become more important.

Interconnect

Microbumps, silicon bridges, TSVs and high-density RDL structures must scale together.

Test and reliability

Inspection, burn-in, thermal cycling and package-level validation become strategic capabilities.

For component distributors and procurement teams, this creates both an opportunity and a warning. The opportunity is a broader range of products and services to support AI infrastructure. The warning is that a part shortage may occur outside the most visible component categories. Package substrates, memory, thermal materials and qualified assembly capacity can become the actual constraint.

10. A practical checklist for buyers and engineering teams

When evaluating AI accelerator supply, looking only at the chip part number is no longer enough. A more useful review should connect the device roadmap with the package and the production ecosystem behind it.

Confirm the package architecture. Identify whether the device uses CoWoS-S, CoWoS-L, EMIB, EMIB-T or another architecture.
Map the HBM configuration. Record HBM generation, stack count, capacity, bandwidth and thermal requirements.
Check production status. Separate a technology demonstration, qualification run, pilot build and stable volume production.
Review the complete bottleneck chain. Ask about wafers, HBM, interposer or bridge supply, substrates, assembly, test and thermal materials.
Plan for package variants. A small change in compute die, HBM count or substrate may require a new qualification cycle.
Use authorized and traceable channels. For high-value AI devices, authenticity, date code, packaging condition and chain of custody are as important as price.

The best procurement question is not simply “Can you supply this accelerator?” It is “Can you support the complete qualified package and its production schedule?”

11. Three possible paths to 2028

No single packaging technology will satisfy every AI product. The market is more likely to develop through a mix of architectures, with the balance determined by workload, customer economics and manufacturing availability.

Scenario	What it looks like	Likely consequence
CoWoS-L remains dominant	Maturity, yield and ecosystem advantages outweigh cost concerns.	CoWoS-L leads high-end GPU and large ASIC packages, while alternatives fill selected niches.
Hybrid competition	CoWoS-L, EMIB-T and other bridge-based options are selected by workload.	Package design becomes a major differentiator for CSPs and accelerator vendors.
Capacity reshapes the market	Customers prioritize qualified capacity and time-to-volume over theoretical peak performance.	Second-source packaging and regional manufacturing partnerships become more valuable.

12. Frequently asked questions

Is CoWoS-L replacing CoWoS-S?

Not completely. CoWoS-S remains suitable for many products. CoWoS-L is better understood as a scaling option for packages that need larger or more flexible combinations of compute dies and HBM.

Will EMIB-T replace CoWoS-L?

That is unlikely across the entire market. EMIB-T can become an important alternative, particularly for selected custom ASICs and programs seeking packaging diversification. CoWoS-L still benefits from maturity, ecosystem depth and production learning.

Why does HBM influence packaging so strongly?

HBM requires very wide, high-speed connections to the compute die. As the number of stacks increases, the package must provide more area, more routing, more power and more thermal management without losing yield.

What should distributors monitor?

Monitor HBM allocation, advanced packaging capacity, substrates, microbumps, silicon bridges, TSV capability, assembly yield, qualification timing and the production ramps of leading GPU and CSP ASIC programs.

Conclusion: the package is becoming the platform

AI acceleration is moving from a race between individual chips to a race between complete systems. The winning solution must connect compute, HBM, power, thermal management and software-defined workloads in a package that can be manufactured at scale.

CoWoS-L currently has the strongest position for the most demanding AI packages because it combines high-density integration with a realistic path beyond conventional interposer scaling. EMIB-T brings credible competitive pressure by offering a bridge-based architecture with different cost and capacity characteristics. Other technologies will continue to develop as AI system requirements become more diverse.

By 2028, advanced packaging will not be a back-end detail. It will be one of the main factors deciding which AI chips can move from design win to reliable volume production.

Sources and editorial note

This article is an independent industry analysis prepared by Chip Seek. Forecasts and company adoption expectations may change as product roadmaps, qualification results and capacity plans evolve.

Chip Seek supplies and sources electronic components for global customers. For product availability, traceability and sourcing support, contact the Chip Seek team.