W25Q32 SPI Layout: Decoupling, Trace Length, and Read Failures
The flash works on the bench at 1 MHz and fails in the product at 50. The cause is rarely the chip: it is the capacitor 15 mm away, the SCK loop around the board, or a control pin left floating.
Quick Answer
- Decoupling: 100 nF within 2–3 mm of the VCC pin, plus 1 µF within 10 mm. A 100 nF alone droops about 0.25 V during a 25 mA, 1 µs burst.
- SCK length: at 1–2 ns edges, 40–80 mm of trace is where ringing and crosstalk start to dominate.
- Termination: 22–33 Ω in series with SCK (at the driver) is the cheapest fix for overshoot.
- Floating pins: /CS, /WP and /HOLD need pull-ups. An unconnected /HOLD explains most "MISO went silent" reports.
1. What the part actually needs
| Parameter | Value | Layout consequence |
|---|---|---|
| Capacity | 32 Mbit (4 MB) | Firmware plus assets, not a file system |
| Supply | 2.7–3.6 V (JV/RV) | Rail must be stable during program/erase |
| SPI clock | 104 MHz class (check variant) | Edge rate, not frequency, sets the length limit |
| Read current | ≈ 4 mA typical | Small, but not zero at 100 MHz |
| Program / erase current | ≈ 25 mA typical | Bursts that empty a small capacitor |
| Erase granularity | 4 KB sector, 32/64 KB block | Erase time dominates update latency |
None of these values is exotic. The failures come from the difference between a datasheet test board and a product board where the flash sits 20 mm from the MCU, the capacitor is on the other side, and /HOLD is unconnected because "it worked on the dev board".
2. Decoupling: the arithmetic is unforgiving
A capacitor supplies current during the time the regulator cannot respond. The droop is set by the charge it must deliver:
dV = I x t / C 25 mA for 1 us, C = 100 nF: dV = 0.025 x 1e-6 / 100e-9 = 0.25 V 25 mA for 1 us, C = 1 uF: dV = 25 mV
A quarter of a volt is enough to take a 3.3 V rail below the flash's minimum during an erase, and the symptom is not "the chip is dead" — it is a failed status poll, a corrupted page, or a boot that hangs until reset.
Distance matters as much as value, because the trace adds inductance in series with the capacitor:
Z = 2 x pi x f x L, L ≈ 1 nH per mm at 50 MHz: 3 mm ≈ 0.9 ohm, 10 mm ≈ 3.1 ohm, 20 mm ≈ 6.3 ohm
By 50 MHz, a capacitor 20 mm away is barely a capacitor. That is why the placement rule is "at the pin", not "near the chip".
Where the current actually comes from
During a read, the flash draws about 4 mA, and the regulator plus the bulk capacitance handle it easily. During program and erase, the internal charge pump draws current in bursts, and the local decoupling has to supply the difference until the regulator loop responds — typically tens of microseconds.
That is why the 100 nF close to the pin and the 1 µF a few millimetres away do different jobs. The 100 nF handles the fast edge; the 1 µF holds the rail through the burst. Removing either one produces a different failure: no 100 nF and the edges couple into the supply; no 1 µF and the rail sags during erase.
If the board already has a large bulk capacitor elsewhere, it does not replace the local 1 µF — the trace between them is the same inductance problem at a different scale.
3. Trace length and edge rate
SPI is not a transmission line at 1 MHz, and it is not a lumped circuit at 50 MHz with a 1 ns edge. The usual rule is that a trace behaves as a transmission line when the round-trip delay exceeds half the rise time:
delay ≈ 6 ps per mm (one way) critical length L > t_r / (2 x 2 x 6 ps/mm) t_r = 1 ns -> L > 42 mm t_r = 2 ns -> L > 83 mm
Below those lengths, the trace is a lumped connection and layout only affects noise coupling. Above them, reflections and crosstalk dominate, and the fix is termination and return-path control rather than "lower the clock".
4. Termination: cheap, effective, often omitted
The usual failure is overshoot on SCK: the driver edge rings above VCC and below ground at the flash pin. A 22–33 Ω resistor in series at the driver end damps it without slowing the edge enough to matter at 50–100 MHz.
When termination is not enough
Series termination fixes the source end. It does not fix a trace that is 150 mm long, a bus with four loads, or a return path that jumps planes. In those cases the options are:
- Lower the clock — the honest fix for long, uncontrolled routing. It costs throughput, not reliability.
- Shorten the bus — move the flash next to the MCU, or use a dedicated SPI bus.
- Buffer or re-drive — a small series buffer at the branch, when the topology cannot change.
A 40 mm bus with 1 ns edges is at the edge of what a simple resistor can rescue; 100 mm is not going to be saved by component selection.
One more practical note: the resistor belongs on the MCU side even when the flash is the only load. If the board has a test point or a header on the SCK net, place the resistor before it, so the stub sees the damped edge rather than the raw driver output.
Do not put the resistor at the flash end — that is a load, not a termination. Put it at the source, close to the MCU pin, and keep the SCK stubs to other devices short or absent.
5. The floating pin that stops the chip
Of all the "random read failure" reports, the most common cause is not signal integrity but a control pin with no defined level. /CS, /WP and /HOLD all need a known state:
- /CS: 10 kΩ pull-up to VCC. If it floats, the chip can be selected by noise.
- /WP: pull-up (or tie high if write protection is not used). A floating /WP can block programming intermittently.
- /HOLD: pull-up. If it floats low, the device ignores the bus and MISO goes high-impedance — exactly the "MISO is floating" symptom.
A classic forum case describes a flash that stops responding after 200 ms to 5 s, with MISO floating, and "works with a 1 MΩ resistor from the power pin to ground" (source). The resistor changes the DC bias of a node that should have had a defined level all along; the real fix is a proper pull-up and a power sequence that does not leave the pin floating during boot.
Boundary: one reported case, not a universal diagnosis. But if MISO floats only sometimes, check /HOLD and /CS before suspecting the SPI driver.
Boot is the worst case
The first 100 ms after power-up is when the flash is most vulnerable: the rail is still rising, the MCU pins are high-impedance, and the flash may already be selected by noise. This is why the pull-ups matter more than they look on a schematic.
A typical failure sequence: the MCU releases reset, drives /CS with a slow GPIO, and reads the JEDEC ID before the rail has settled. If the flash answers with 0xFF or 0x00, the bootloader may conclude the part is absent and jump to a recovery path. The board then "randomly" fails to boot, which looks like a firmware bug.
Two cheap defences: a 10 kΩ pull-up on /CS so the device is deselected while the MCU is in reset, and a bootloader that retries the ID read a few times with a short delay. Neither costs anything on the BOM.
6. Shared buses and crosstalk
It is common to share SCK, MOSI and MISO between the flash, an SD card and a display. Each extra device adds:
- Stub length on SCK (bad above a few millimetres at fast edges)
- Capacitive load (slows edges, increases dynamic current)
- A second chip-select that must be deasserted cleanly
If the bus must be shared, route SCK as a daisy chain through the devices rather than a star, keep stubs under 5 mm, and place the series resistor before the first branch. If the flash is only used at boot, consider a dedicated bus.
Coupling is proportional to the parallel length and inversely related to separation. Two traces 0.2 mm apart running together for 30 mm will couple far more than the same traces at 0.5 mm. In practice: keep SCK away from MISO and from any analog or reset line, and never run SCK parallel to a connector ribbon.
The other crosstalk source is the ground return. If SCK and MISO share a narrow return path, the SCK current modulates the reference for MISO. A continuous plane under both, with no slot between them, is worth more than any component change.
7. What the symptom tells you
| Symptom | Likely cause | Fix |
|---|---|---|
| MISO floats, works when cold | Floating /HOLD or /CS | 10 kΩ pull-ups, check boot sequence |
| Fails only during erase | Rail droop on 25 mA bursts | 1 µF bulk at the pin, 100 nF closer |
| Random bit errors at speed | SCK ringing / crosstalk / long stub | Series 22–33 Ω, shorten SCK, add return |
| Works at 1 MHz, fails at 50 | Edge-rate effects, not logic | Termination + impedance-controlled routing |
| Slow reads, long polls | Wrong dummy cycles or mode bits | Check the command set for your variant |
8. Two layouts, same schematic
| Rule | Reason | Typical mistake |
|---|---|---|
| 100 nF at the VCC pin | Supplies high-frequency current | Cap on the far side of the package |
| 1 µF bulk within 10 mm | Covers erase bursts | Only 100 nF fitted |
| Pull-ups on /CS, /WP, /HOLD | Defined state at boot | "It worked without them" |
| Function pins not left floating | Noise can select or hold the chip | HOLD left open on a 8-pin part |
| Continuous ground under SCK | Return current follows the signal | Plane split under the bus |
| Series 22–33 Ω on SCK | Damps ringing | Resistor at the flash end |
9. Verifying it
What good looks like on a scope
At the flash pin, SCK should show a single clean edge with less than about 10 % overshoot and no second transition. If you see a step or a ring that crosses the threshold twice, the receiver can double-clock, and the error appears as a data shift rather than a dead bus.
Measure VCC at the flash pin, not at the regulator. A 100 mV droop on the scope during erase is already a warning; a 300 mV droop is a design change, not a capacitor tweak.
| Check | Pass | If it fails |
|---|---|---|
| VCC at the pin during erase | ≥ 3.0 V, droop < 100 mV | Add 1 µF, move 100 nF closer |
| SCK overshoot | < 10 %, single edge | 22–33 Ω at the driver; shorten trace |
| /CS, /WP, /HOLD at power-up | Defined high | 10 kΩ pull-ups |
| JEDEC ID read | Correct ID, 10/10 boots | Add retry and rail-settle delay |
| Read at full clock, 1 hour, hot | 0 errors | Treat as signal integrity, not firmware |
- Scope SCK and MISO at the flash pin with a short ground lead; look for overshoot and ringing, not just logic levels.
- Measure VCC at the flash pin during an erase; a droop below 2.7 V explains most "random" failures.
- Check /CS, /WP and /HOLD DC levels at power-up with a meter; any floating pin is a future field return.
- Run the SPI clock at the intended rate for an hour at temperature, not for ten seconds on the bench.
- If using quad mode, verify the dummy-cycle setting for the exact variant; wrong mode bits look like signal integrity.
Our W25Q32RV is stocked in SOIC-8, and the cross-reference guide covers package and voltage differences between vendors. For the ESD side of the same connector, see the USBLC6 layout guide, and for incoming inspection of flash, our traceability process. Other NOR densities and packages are listed in the memory collection.
10. Design review in three questions
- How far is the capacitor from the VCC pin? Under 3 mm, or it is not decoupling.
- How long is SCK, and what is the edge rate? 40 mm is the limit at 1 ns edges.
- Are /CS, /WP and /HOLD driven or pulled at power-up? If any is floating, the design is not finished.
11. FAQ
Can I run W25Q32 at 1 MHz to avoid layout problems?
Yes, and it will hide them. The risk is that the product ships, someone enables a faster mode, or a batch with faster edges arrives. Layout for the speed you intend to use, with margin.
Is one 100 nF capacitor enough?
For read-only use at low clock, usually. For programming, add 1 µF: a 25 mA burst for 1 µs takes 25 nC, which is a quarter of the charge in 100 nF at 3.3 V.
Does the series resistor slow the bus?
Not meaningfully at 50–100 MHz with 22–33 Ω and short traces. It forms an RC with the trace capacitance, but the edge still arrives well within a clock period.
Why does my flash work on a dev board and fail on my board?
Dev boards usually have the flash close, a ground plane under it, and pull-ups fitted. Production boards often do not. Compare capacitor distance, SCK length and pull-ups first.
Do I need a pull-up on /CS if the MCU drives it?
Yes. During reset, boot and programming, the MCU pin is high-impedance, and a floating /CS can select the flash at the wrong moment.
Can I share SCK with an SD card?
You can, but the stub and the extra capacitance change the edges. Keep the stub short, place the series resistor before the branch, and test at the highest clock you will use.
Does the flash need a reset supervisor?
Not for the flash itself, but a supervisor helps the system: it holds the MCU in reset until the rail is valid, so the first ID read happens after the flash is ready. Without one, add a delay in the bootloader instead.
Why do some boards need a 1 MΩ resistor to work?
They do not — that resistor usually biases a floating node that should have had a pull-up. It is a symptom-level fix. Find the pin that is floating (/HOLD, /WP or /CS) and give it a defined level.
12. Sources
- Winbond W25Q32JV datasheet (Rev J) — 2.7–3.6 V, 4 KB sectors, SPI modes, program and erase currents.
- Texas Instruments, High-Speed Layout Guidelines for Signal Conditioners and USB Hubs (SLLA414) — decoupling and return-path practice.
- Electronics StackExchange, SPI flash failing without a 1 MΩ resistor (2017).
- EEVblog forum, Weird SPI flash problem (W25Q32JV).
Debugging an SPI flash?
Send the schematic excerpt and layout distance. We will tell you whether the failure is decoupling, termination or a floating pin before you respin.
