Decoupling Capacitor Selection: Bias, SRF, Distance

Decoupling Capacitor Selection: Dielectric, Bias, and Distance

A 10 µF capacitor is not 10 µF. At rated voltage it may be half that, and above its self-resonant frequency it is an inductor. The three numbers that matter are not on the front page.

Quick Answer

Dielectric: X7R for decoupling, C0G for filters and timing, X5R only when the bias is low.
DC bias: a 10 µF X5R at 25 V can lose 60–80 % of its capacitance.
Self-resonance: 100 nF 0402 resonates near 25 MHz; above that it is inductive.
Distance: 1 nH per mm. Five millimetres is a different component.

1. Dielectrics are not interchangeable

Class	Stability	Use
C0G / NP0	Excellent, no bias loss	Filters, oscillators, timing
X7R	±15 % over temperature	General decoupling
X5R	±15 %, worse bias	Bulk where space is tight
Y5V	−80 % over temperature	Avoid for anything critical

The same nominal value in C0G and Y5V can differ by a factor of five in circuit. The price difference is small; the design consequence is not.

Case	Nominal	In circuit (estimate)
10 µF X5R 25 V at 12 V	10 µF	4–5 µF
10 µF X7R 16 V at 12 V	10 µF	5–6 µF
10 µF C0G 25 V at 12 V	10 µF	10 µF (larger case)

2. DC bias: the hidden derating

Effective capacitance versus DC bias for C0G, X7R and X5R — Figure 1 — Illustrative: X5R and X7R lose capacitance with bias; C0G does not.

This is the most common reason a decoupling network that looks generous on paper is marginal in circuit. A 10 µF X5R 25 V part at 12 V may measure 4 µF; a 10 µF X7R 16 V at 12 V may measure 5 µF. The datasheet value is measured at 0 V.

Practical consequence: for a rail within 50 % of the capacitor's rating, assume 50 % of the nominal value unless the vendor publishes a bias curve. For C0G, use the nominal value.

3. Above self-resonance it is an inductor

Impedance versus frequency for 1 uF, 100 nF and 10 nF capacitors — Figure 2 — Each capacitor has a minimum impedance at its SRF; above it, ESL dominates.

SRF = 1 / (2 pi sqrt(L x C))

100 nF, 0.4 nH (0402): 25 MHz
1 uF,   0.8 nH:        5.6 MHz
10 nF,  0.8 nH:        56 MHz

Below SRF the impedance falls with frequency; above it, the ESL sets the impedance and rises. That is why a 1 µF part does not replace a 100 nF part at high frequency, and why the small capacitor should be closest to the pin.

Two capacitors in parallel do not simply add: between their self-resonant frequencies the pair can show a local impedance rise (anti-resonance), which is why a small C0G next to the pin and a larger X7R nearby is a better pair than two identical parts. The exact shape depends on ESR, which damps the peak.

Impedance of the same 100 nF value in 0402 and 1206 packages — Figure 3 — Same value, different package: the larger case has more ESL and a lower SRF.

4. Distance is inductance

Voltage transient versus capacitor distance from the IC pin — Figure 4 — Illustrative: a 0.5 A step in 1 ns across 1 nH/mm. Five millimetres is 0.5 V.

The capacitor supplies the current the regulator cannot respond to, and the trace between them is an inductor in series with that supply. The rule is placement first, value second: a 100 nF at the pin beats a 10 µF at the far end of the board for high-frequency transients.

Vias are part of the distance. A single via to the ground plane adds roughly 0.5–1 nH; two parallel vias halve that. For a high-current rail, the return path through the plane matters as much as the capacitor value.

5. Pick by role

Four capacitor roles: bulk, local decoupling, high frequency, analog reference — Figure 5 — Four jobs, four different parts. One value cannot do all four.

Role	Typical	Mistake
Bulk input	10–100 µF, low ESR	Using a tiny case for a large value
Local decoupling	100 nF, 0402/0603	Placed 10 mm away
High frequency	10–100 nF, C0G	Using X5R for a filter
Analog reference	1–10 µF, low leakage	High-leakage electrolytic

For switching converters, the input capacitor also carries ripple current; see the buck layout guide for that calculation. For the SPI and I²C side, the flash layout guide shows the same placement logic at a different frequency.

5b. A practical default

Rail	Default network
3.3 V logic, low current	100 nF per pin, 10 µF per rail
5 V logic, mixed loads	100 nF per pin, 22 µF per rail
Switching converter input	10 µF ceramic close, plus bulk
Analog reference	1 µF C0G or low-leakage, close

6. Checklist

Choose the dielectric by role, not by price.
Check the DC-bias curve at the working voltage.
Check the SRF against the frequencies you need to decouple.
Place the smallest capacitor closest to the pin.
Add vias to the ground plane, one per capacitor minimum.
For large values, check ripple current and case size.

7. FAQ

Is a bigger capacitor always better?

No. Larger values have more ESL and lower SRF, and they do not replace a small capacitor at high frequency.

Why does my 10 µF measure 4 µF?

DC bias. Class II ceramics lose capacitance as the voltage approaches the rating. C0G does not.

Can I use one capacitor for everything?

Not well. Bulk, local and high-frequency roles have different requirements.

Does capacitor aging matter?

For class II ceramics, capacitance drifts slowly with time and is restored by soldering heat. For precision timing, use C0G.

How close is close enough?

Within a few millimetres for the local decoupling capacitor, with a short return to the plane. If in doubt, move it closer.

Do I need a capacitor on every power pin?

Usually yes, one small capacitor per pin, plus the bulk capacitor shared by the rail.

8. Sources

Manufacturer ceramic capacitor datasheets — DC-bias curves, temperature coefficients, ESR/ESL.
Application notes on decoupling and PDN design (TI, Analog Devices, Murata, TDK).
JEDEC/IPC component and assembly standards for package and mounting context.