Gate Resistor and Switching Loss: One Part, Two Effects

The gate resistor is the simplest part on a power board and the one that decides both how much the switch rings and how much heat it makes. The two effects pull in opposite directions.

Quick Answer

Small Rg: fast edges, low switching loss, more ringing and EMI.
Large Rg: clean edges, less ringing, more switching loss and heat.
Split path: a diode across Rg for fast turn-off and controlled turn-on.
Measure: gate plateau, VDS overshoot and the V×I crossing area — not a guess from the datasheet.

1. What the resistor actually controls

Gate charge curve showing the Miller plateau — Figure 1 — Gate charge, not capacitance, determines how long the transition takes at a given drive current.

Ipk  = Vdrive / (Rg + Rdriver)
t_sw ~ Qg / Ipk
Psw  ~ 0.5 x VDS x ID x (tr + tf) x fsw

The gate behaves like a charge bucket: the driver pushes Qg through Rg, and the transition time is roughly charge divided by current. Doubling Rg halves the current, doubles the time, and doubles the switching loss.

The driver's internal resistance is part of the total, and it is not small: a typical MCU pin is tens of ohms, a dedicated driver is a few ohms. That is why replacing a GPIO with a gate driver changes the edge more than changing Rg by a few ohms.

Qg	Rg total 10 Ω	Rg total 22 Ω
5 nC	5 ns	11 ns
10 nC	10 ns	22 ns
30 nC	30 ns	66 ns

2. The trade, in numbers

Switching loss versus total gate resistance for 10 V and 5 V drive — Figure 2 — Example: 24 V, 5 A, 200 kHz, Qg 10 nC. Drive voltage matters as much as resistance.

Rg 10 ohm, 10 V drive: Ipk 1 A, t 10 ns, Psw ~ 0.24 W
Rg 22 ohm: Ipk 0.45 A, t 22 ns, Psw ~ 0.53 W
Rg 10 ohm, 5 V drive: Ipk 0.5 A, t 20 ns, Psw ~ 0.48 W

Two lessons: the resistor is not the only lever — the drive voltage is — and the difference between 10 Ω and 22 Ω is roughly 0.3 W, which in a small package is 15 K.

3. Ringing

Illustrative drain-source overshoot with small and large gate resistance — Figure 3 — The same node with 2 Ω and 22 Ω: the faster edge rings higher.

Ringing is a loop problem: the gate loop and the power loop both have inductance, and the edge excites them. Rg damps the gate loop directly and slows the drain edge, which reduces the energy injected into the power loop. A snubber across the switch damps the power loop without slowing the gate — a different tool for a different loop.

4. Split the path

Gate resistor with a diode for fast turn-off — Figure 4 — Turn-on through Rg, turn-off through the diode: controlled dv/dt on the way on, fast off.

Turn-on and turn-off do not need the same speed. A slow turn-on reduces EMI and diode reverse recovery; a fast turn-off reduces the switching loss and avoids shoot-through. The diode bypass gives both, at the cost of one part and a little layout care.

The diode must be fast — a small signal diode with nanosecond recovery, not a rectifier. Place it close to the resistor so the turn-off loop stays short; a long diode path re-introduces the inductance you were trying to avoid.

Goal	Change	Cost
Lower EMI	Larger Rg on turn-on	More switching loss
Lower loss	Smaller Rg, stronger driver	Ringing, overshoot
Both	Split Rg with diode	One extra part, layout
Damp the power loop	RC snubber	Efficiency, board space

5. Choosing a starting value

Situation	Starting Rg
Small FET, low current, < 100 kHz	10–22 Ω
Medium FET, 1–5 A, 100–300 kHz	4.7–10 Ω
Large FET, > 5 A, high frequency	2.2–4.7 Ω, with a driver
EMI-sensitive product	Larger on turn-on, diode on turn-off

Start at the upper end of the range, measure the edge and the loss, then reduce until the ringing or the EMC margin stops you. That is faster than calculating and hoping.

5b. Checks before you commit

Check	Pass
VDS overshoot	Below 80 % of rating
Gate plateau	Flat, no high-frequency ring
Switching loss	Within the thermal budget at max ambient
EMI	Margin at the worst-case load
Dead time	No shoot-through at temperature extremes

6. Measured, not estimated

Three measurements: gate voltage, drain-source voltage, drain current — Figure 5 — Align gate, VDS and ID in time; the overlap area is the loss.

Gate voltage: confirm a flat plateau and no ringing at the pin.
VDS: check overshoot against the rating with margin; measure at the worst-case load and temperature.
Drain current: a current probe or a shunt; the V×I overlap is the switching energy per edge.
Compute the loss from the measured areas, not from the datasheet's typical tr/tf.

For the surrounding thermal budget, the MOSFET selection guide covers the conduction and package side; for the loop that rings, the buck layout guide covers the hot loop.

7. FAQ

Does a larger gate resistor always reduce EMI?

It reduces the edge rate, which usually helps, but it also increases switching loss and can worsen low-frequency ringing if the layout loop is large. Layout first, resistor second.