Crystal Startup: Load Capacitance, Negative Resistance, and Probe Traps

A crystal oscillator that starts on the bench and fails at −20 °C is not a mystery. It is a margin problem, and there are two measurements that expose it before the product ships.

1. What the capacitors actually do

The crystal is specified for a load capacitance CL. The two external capacitors are in series from the crystal's point of view, plus the stray capacitance of the PCB and pins:

CL = (C1 x C2) / (C1 + C2) + Cstray

with C1 = C2 = C:
CL = C/2 + Cstray
C  = 2 x (CL - Cstray)

Two consequences. First, using 8 pF capacitors for an 8 pF crystal is wrong: it gives CL ≈ 7 pF at best and usually less, pulling the frequency high. Second, a 5 pF stray assumption changes the answer by 4 pF per capacitor, which is why layout and package choice matter before you tune anything.

Estimating the stray capacitance

Stray capacitance is the sum of the MCU pin capacitance (typically 2–5 pF), the crystal pad capacitance, and the trace to ground. A short, narrow trace on a ground plane adds less than 1 pF; a long trace beside a switching node adds several.

The practical estimate is 3 pF for a compact layout and 5 pF for a larger one. If the design is tight on frequency, measure it: fit known capacitors, measure the resulting frequency, and solve for the effective CL. That takes one board and ten minutes, and it removes the largest unknown in the tolerance stack.

Layout rules are simple and often skipped: keep the crystal within a few millimetres of the pins, put the load capacitors between the crystal and the ground pin, keep the traces short and symmetric, and do not route anything switching underneath. A ground guard ring around the crystal is cheap and keeps hand proximity from shifting the frequency. The same discipline applies to high-speed buses; see the SPI layout guide for the trace and return-path side.

2. Frequency error: what a picofarad costs

Near CL, the pulling sensitivity of a typical crystal is about 10–12 ppm per pF. That sounds small until you multiply it by the tolerance stack: crystal ±20 ppm, capacitors ±5 %, stray estimate ±2 pF.

2 pF error x 12 ppm/pF = 24 ppm
plus crystal tolerance   = 20 ppm
worst case              ~ 44 ppm

For a UART or USB clock, tens of ppm is irrelevant. For an RTC or a radio reference, it is the whole budget — which is why 32.768 kHz designs often use a crystal with integrated load capacitors and a factory-trimmed tolerance, such as the an integrated-crystal RTC module.

A useful sanity check: 44 ppm is about 3.8 seconds per day. That is acceptable for a data logger and unacceptable for a time-of-day clock that must stay within a minute per year.

3. Startup: the measurement that predicts cold failures

A crystal oscillator starts because the amplifier provides more small-signal gain than the resonator loses. The margin is expressed as negative resistance: the circuit's equivalent resistance looking into the amplifier, which must be larger than the crystal ESR by a comfortable factor.

Measure -R:
1. Add a series resistor Rs in series with the crystal
2. Increase Rs until oscillation stops
3. -R ~ Rs(stop) + ESR
4. Require -R >= 5 x ESR

Running the test reliably

Cut one of the crystal leads and insert a small potentiometer or a set of fixed resistors. Start at zero, increase in steps, and at each step power-cycle the board: the test is about starting, not about whether a running oscillator keeps running.

Record the resistance at which it fails to start, then add the crystal ESR. Repeat at the lowest temperature the product will see — mist in a freezer is a practical way to get −20 °C without a chamber. A design that passes at 25 °C and fails at −20 °C has a margin problem, not a crystal problem.

Why 5×: the oscillator gain falls with temperature and supply voltage, and the crystal ESR rises. A design with 2× margin works at 25 °C and fails on a cold morning. The test is simple enough to run on every prototype, and it is the only measurement that predicts the failure mode you cannot reproduce on the bench.

The same margin can be estimated from the transconductance requirement:

gm_crit = 4 x ESR x (2 pi f)^2 x (C0 + CL)^2

ESR 60, f 8 MHz, C0 5 pF, CL 8 pF:
gm_crit ~ 0.10 mA/V
design target: 5x = 0.5 mA/V

Microcontroller datasheets usually quote the oscillator transconductance, so this is a paper check you can do before the board exists. If the number is close, choose a lower-ESR crystal or a different oscillator pin.

4. Startup is an exponential

Oscillation builds exponentially from noise. A healthy circuit reaches full amplitude in hundreds of microseconds; a marginal one takes milliseconds and may stall when the gain drops with temperature. This is why "it starts" is not the test — the test is how fast, and at what temperature.

Typical expectations for an 8 MHz oscillator at 3.3 V: full amplitude within 1–5 ms. If it takes 20 ms, the margin is thin even if it eventually starts. If it takes 200 ms, the design is one cold morning away from a boot failure.

5. Probe loading: the trap that hides itself

A typical passive probe adds 10–15 pF. On an 8 pF oscillator that changes the load to 18–23 pF, pulls the frequency by over 100 ppm, and often stops the circuit entirely — leading to the conclusion that the oscillator is broken.

Three ways to measure without ruining the measurement:

• Buffer the signal: enable the clock output (MCO/CLKOUT) and measure that pin, which is driven and not part of the oscillator loop.
• Use an active probe with 1 pF or less, or a FET probe.
• Measure indirectly: read the timer or RTC counter over time and compare with a reference; frequency accuracy can be measured without touching the oscillator.

6. Drive level: the specification nobody checks

Crystals are rated for a maximum drive level, typically 100 µW. Exceeding it ages the crystal faster and can crack the resonator:

I  ~ 2 pi f x CL x Vpp
DL = ESR x I^2

8 MHz, CL 8 pF, 3.3 Vpp, ESR 60:
I  ~ 1.33 mA
DL ~ 106 uW   (at the 100 uW rating)

That estimate is at the rating, not comfortably below it. If the oscillator runs at a higher supply or with a larger CL, add a series resistor between the amplifier output and the crystal, or choose a crystal with a higher drive-level rating.

Sizing the resistor is iterative: start with 100–470 Ω, re-check startup and drive level, and keep the frequency error acceptable. The resistor trades drive level for negative resistance, so a design that was marginal on startup may need a different crystal rather than a larger resistor.

7. Failure patterns

8. Prototype checklist

A typical failure, step by step

A 32 MHz USB-capable MCU starts on the bench and fails to enumerate when cold. The crystal is 8 pF, the caps are 8 pF (copied from a reference design), the ESR is 50 Ω, and the load is therefore about 7 pF — 12 ppm high before tolerance. The negative resistance measures 120 Ω at 25 °C, which is 2.4 × ESR: below the 5× rule.

Two fixes are possible. Change the caps to 10 pF (frequency correct, no effect on margin), and choose a lower-ESR crystal or a different oscillator setting for the margin. The frequency error alone would not stop enumeration; the startup margin is what fails cold.

For the clock-line layout around the oscillator, the same principles as the I2C timing guide apply: short traces, a solid return, and a probe that does not change the circuit. Our traceability process covers date-code and lot checks on crystals.

9. FAQ

Why do I need 10 pF caps for an 8 pF crystal?

Because the two capacitors are in series and the PCB adds stray capacitance. With 3 pF stray, C = 2 × (8 − 3) = 10 pF per side.

Can I use the same capacitor value for any crystal?

No. The value comes from the crystal's CL and the board's stray capacitance. Copying a value from a reference design is the most common source of 30–60 ppm errors.

What is negative resistance and why 5×?

It is the small-signal gain expressed as a resistance. The 5× rule covers temperature, supply and ESR variation; 2× works on the bench and fails in the field.

Why does the oscillator stop when I connect a probe?

The probe adds 10–15 pF, which changes the load and can reduce the loop gain below unity. Measure a buffered clock output or use an active probe.

Does a higher supply voltage improve startup?

Usually yes, because the inverter's transconductance rises with supply. That is also why a design that works at 3.3 V can fail at 1.8 V.

How do I measure frequency without loading the oscillator?

Use the MCU's clock output, or count the RTC/timer over a known interval against a reference. Both avoid touching the oscillator node.

Does the capacitor type matter?

Use C0G/NP0 ceramic. X7R capacitors lose capacitance with DC bias and temperature, which changes the load and therefore the frequency. The cost difference is small and the behaviour is predictable.

Can I omit the load capacitors if the MCU has internal ones?

Only if the MCU provides the exact value and the datasheet says so. Internal capacitors are coarse and vary between parts, which is acceptable for some UARTs and not for RTCs.

10. Sources

• Texas Instruments, Use of the CMOS Unbuffered Inverter in Oscillator Circuits (SZZA043) — Pierce oscillator, negative resistance, drive level.
• STMicroelectronics, AN2867 — oscillator design guide for STM32 (negative resistance method and safety factor).
• Epson, crystal application notes — load capacitance, drive level and frequency pulling.