1. What the report actually says

On September 30, Taiwan's Economic Daily reported, citing sources in the semiconductor equipment industry, that TSMC intends to establish a manufacturing base beyond its Phoenix, Arizona campus and build six additional advanced wafer fabs there. The report put the potential investment above the $265 billion already associated with TSMC Arizona, and identified Dallas and the wider North Texas region as the most likely location.

The sourcing matters as much as the claim. Equipment suppliers are among the first to see a fab plan, because tool lead times force early capacity reservations. They are also among the last to see a final board decision. A report built on their visibility is a signal about intent and site preparation, not a signed commitment.

TSMC has not confirmed the plan. Government officials quoted in Taiwanese media said Texas has a semiconductor industrial base and could be one of the locations under evaluation, but that any investment must be decided by TSMC's board and announced by the company. The same officials reiterated that research and development remains based in Taiwan, and that the most advanced process development will stay there.

That combination — supply-chain signal, official non-denial, and a reaffirmation that R&D stays in Taiwan — is the pattern that has preceded every previous TSMC expansion announcement. It is worth treating as a leading indicator rather than a fact.

2. The Arizona ladder: $65B, then $165B, then $265B

To understand the scale of a six-fab second site, it helps to look at how the first one grew.

Between 2020 and 2024, TSMC began construction on three fabs in Arizona with a combined investment of roughly $65 billion. The first, a 4nm facility, entered mass production in 2024. The second, a 3nm fab, is scheduled for mass production in the second half of 2027 — a year earlier than the original 2028 plan. The third broke ground in April 2025, is expected to start production in 2028 on N2 and A16, and should reach volume output around 2030.

In March 2025, chairman and CEO C.C. Wei announced an additional $100 billion: three more fabs at roughly 20,000 to 25,000 wafers per month each, two advanced packaging facilities — AP1 for SoIC and AP2 for CoPoS — and a large R&D center. That took the U.S. commitment to $165 billion.

In July 2026, at the second-quarter earnings call, TSMC added another $100 billion for Arizona, bringing the total to $265 billion, or roughly RMB 1.8 trillion. That money is earmarked for four or more additional fabs plus advanced packaging lines, taking the U.S. cluster toward ten fabs and two packaging facilities, focused on 2nm and below.

The pattern is a ladder, not a single decision. Each rung was justified by customer demand, and each rung made the next one easier to justify, because a larger cluster spreads the fixed costs of construction, utilities and workforce development. A second site in Texas would be the first time the ladder leaves Arizona — and the first time TSMC has to duplicate a cluster rather than extend one.

3. Why a second site instead of more Phoenix

The instinctive question is why TSMC would build somewhere new when it already has a campus with ten fabs planned. The answer is that fabs are not the only thing a site consumes.

A leading-edge fab is an industrial customer of extraordinary scale. It needs large volumes of ultrapure water, redundant high-voltage power, specialty gases, and a workforce that can be recruited, trained and retained in a tight labor market. Concentrating more and more capacity on one site produces reverse economies of scale: the more fabs you add, the more strained the shared infrastructure becomes.

Dispersing capacity is a risk-management decision as much as a cost decision. A second cluster reduces exposure to a single water basin, a single grid interconnection, a single local labor pool and a single set of permitting bottlenecks. It also gives TSMC a second political constituency in Washington, which matters when subsidy terms are renegotiated.

There is a supply-chain argument too. Arizona's ecosystem is still maturing. North Texas already has a denser base of semiconductor manufacturing, equipment, materials and photonics companies. Putting a cluster where suppliers already are shortens qualification cycles and reduces the number of vendors who have to open a new site to serve one customer.

The water and power arithmetic

A leading-edge fab consumes water at a scale that surprises people outside the industry. Ultrapure water is used for cleaning wafers between process steps, and the treatment system that produces it is itself a significant capital item. TSMC's Arizona site was designed with high recycling rates, but recycling reduces consumption rather than eliminating it, and the residual demand is still measured in millions of gallons per day once multiple fabs are running.

Power is the second constraint. A cluster of ten fabs draws a load comparable to a mid-sized city, and it needs redundancy: a single interruption can scrap wafers worth millions of dollars. Interconnection queues in the United States have become a bottleneck in their own right, with large industrial customers waiting years for grid upgrades. Siting a second cluster in a different grid region is, in part, a way to avoid competing with your own Phoenix load.

Texas has abundant land and a large industrial power base, but it also has drought history and a grid that has been tested by extreme weather. The site-selection process will therefore look less like a real-estate decision and more like an infrastructure negotiation: water rights, treatment capacity, substation timing and long-term supply contracts. Those negotiations take longer than land options, which is one reason a reported plan can precede an announcement by years.

4. Why Dallas and North Texas

Wells Fargo analysts have described the Dallas–Fort Worth corridor — often called the Silicon Prairie — as a reasonable location for a second campus. The region already hosts manufacturing from Texas Instruments, Samsung, Coherent and Terafab, and TSMC operates a design service center in Austin.

The cluster is not just fabs. North Texas has built up wafer manufacturing, equipment, materials, optical communications and electronics manufacturing over two decades. That matters for the unglamorous parts of a project: the companies that calibrate tools, supply spare parts, handle chemical waste and train technicians.

Land, power and talent are the three variables analysts cite most often. Texas has abundant land and a grid that, whatever its reliability debates, can support large industrial loads. It has engineering schools and a growing semiconductor workforce. And it has a state government that has made advanced manufacturing a priority.

The counter-argument is water. Advanced fabs recycle heavily, but they still need a reliable supply, and Texas has experienced severe drought cycles. Any site decision will have to answer questions that Phoenix has already answered — which may be one reason the plan is described as under evaluation rather than decided.

5. The policy layer nobody puts in the press release

The expansion curve is not purely commercial, and the reporting makes that explicit.

U.S. Commerce Secretary Howard Lutnick has said Washington pressured TSMC to increase investment, citing diversity, equity and inclusion provisions, and used the threat of 100% tariffs to push the company toward its initial U.S. commitment. Reports also described an offer to reduce tariffs on Taiwanese goods from 20% to 15% in exchange for a commitment to build at least five more semiconductor plants in the United States. Taiwanese media characterized the arrangement in blunt terms.

Analysts have also pointed to threats of tariffs as high as 200% on chipmakers that do not build in the United States as a factor behind the second-campus planning. Because later fabs would use more advanced processes, the investment is expected to exceed the first campus.

For buyers, the policy layer matters because it changes the economics of where capacity lands. A fab built to satisfy a tariff threat has a different utilization strategy than a fab built to serve a customer contract. It may run at lower initial loading, take longer to reach cost targets, and be priced to recover a higher capital base — all of which eventually shows up in wafer prices.

6. The cost problem: 2x to 5x

TSMC has been unusually candid about the cost gap. Building in the United States costs roughly two to five times as much as building in Taiwan. Depreciation per wafer is about four times higher. Labor costs are more than double.

Those numbers compound. A fab with four times the depreciation and twice the labor must either charge more per wafer, run at higher utilization, or accept lower margins. For leading-edge nodes, where TSMC's pricing power is strongest, the gap can be absorbed. For mature nodes, it cannot.

Workforce is the second half of the cost problem. The Arizona site has around 2,200 employees, about half of whom have been assigned from Taiwan. That ratio is a measure of how much tacit knowledge is still being transferred, and it is expensive: relocated engineers cost more, and they are needed in Taiwan too.

Recruiting locally is a long-term project. The DEI requirements that Washington has cited add another layer of tension, because they shape hiring criteria at the same time the company is trying to replicate a specific engineering culture. Neither side of that debate is resolved, and it will influence how quickly a second cluster can be staffed.

7. What six fabs would actually produce

If the report is accurate, the capacity math is straightforward. At 20,000 to 25,000 wafers per month per fab — the range TSMC used for its March 2025 additions — six fabs would add 120,000 to 150,000 wafers per month of advanced capacity.

That is a large number in isolation and a moderate one in context. TSMC's total 2nm capacity is expected to reach around 120,000 wafers per month by the end of 2026, according to reports, up from earlier estimates of 90,000 to 100,000. A six-fab campus would roughly double that figure once fully ramped, but ramp takes years: construction, tool move-in, process qualification and customer qualification each consume time.

Two details in that table matter more than the totals. First, the Arizona plan already includes packaging — AP1 and AP2 — which means the U.S. cluster is being designed as a self-contained flow rather than a wafer source feeding Asian packaging. Second, the Texas plan, as reported, is wafer-only. If that holds, North Texas would depend on Arizona or Taiwan for advanced packaging, at least initially.

Tool lead times and the ramp curve

One reason announcements and output are separated by so many years is that the equipment itself is scarce. Extreme ultraviolet lithography tools are built to order, and the lead time from order to installation has historically been measured in quarters, not weeks. A new fab must reserve tools long before the building is finished, which is why equipment suppliers often know about a project before the public does.

The ramp is also sequential rather than parallel. A fab moves from construction to tool installation, then to process qualification on test wafers, then to customer qualification, and only then to volume production. Each stage has its own yield learning curve. Even a fab that starts construction in 2028 would not contribute meaningful volume before 2030, and its first year would be consumed by qualification runs rather than sellable output.

That timing is why the reported Texas plan should be read as 2030+ capacity. It affects long-term allocation and supplier investment, not the supply that will be negotiated for 2027 or 2028.

8. Packaging is the real constraint

For AI accelerators, the bottleneck stopped being lithography some time ago. It is packaging.

CoWoS — chip-on-wafer-on-substrate — is the 2.5D platform that puts logic dies and HBM stacks on an interposer. Every high-end AI accelerator depends on it, and capacity has been sold out for years. TSMC's roadmap, presented at its China Technology Forum, is built around one word: bigger.

The roadmap on the slide is a schedule, not a slogan. In 2024, TSMC shipped a 3.3-reticle package with eight HBM3 stacks. The 5.5-reticle version, with twelve HBM3E or HBM4 stacks, is in production in 2026 with yields above 98%. A 9.5-reticle package with twelve HBM4E stacks follows in 2027. The 14-reticle version with twenty HBM5 stacks is scheduled for 2028, and a package larger than 14 reticles with twenty-four HBM5E stacks for 2029.

Each step increases the amount of silicon that must be handled, bonded and tested as a single unit, and each step raises the capital intensity of the packaging line. It also raises the value at risk in a single assembly step: a package carrying twenty HBM stacks is worth far more than the wafer that fed it.

SoIC represents the other direction: denser rather than larger. Where CoWoS is 2.5D, SoIC is 3D, with 56 times the interconnect density and five times the power efficiency, according to TSMC. The pitch ladder is equally explicit: 9µm on N7 in 2023, 6µm on N5 entering volume production in 2025, 6µm on N4 and N3P, 5µm on N2P in 2028, and 4.5µm for A14 stacking in 2029. Vertical connection is approaching the density of horizontal routing.

That is why the Taiwan packaging build-out matters more than the headline fab count. Chiayi AP7 carries more than NT$500 billion of investment. Phase one includes P1 and P2, targeted for 2027. P1 is described as an Apple-exclusive WMCM line; P2 and P3 focus on CoWoS; CoPoS is expected in P4 or P5. The full site is scheduled to reach volume between late 2028 and 2029.

The HBM coupling problem

Package scaling is not only a packaging problem. A 14x-reticle CoWoS package integrating 20 HBM stacks consumes far more memory and substrate area per accelerator than today's parts. The package becomes a system-level bill of materials: logic dies, HBM stacks, interposer, substrate, thermal interface and assembly yield all interact.

That coupling is why packaging capacity and memory supply have to be planned together. If HBM supply grows more slowly than packaging capacity, the packaging lines run below capacity. If packaging lags, HBM sits in inventory. TSMC's roadmap — 5.5x in production, 14x with 20 stacks in 2028, 24 stacks in 2029 — is effectively a statement about how much HBM the industry should expect to consume per accelerator.

Yield compounds the effect. TSMC reports 98% yield on the 5.5x version, which is remarkable for a complex assembly. But as package area grows, the number of known-good die per package rises, and the cost of a failed package rises with it. Larger packages push more value through a single assembly step, which makes packaging yield a financial variable rather than a technical footnote.

9. Chiayi phase three: five more packaging fabs

On September 23, Taiwanese authorities published the information disclosure and public comment procedure for the Chiayi Science Park expansion — widely referred to as Chiayi phase three. According to the plan, TSMC intends to add five more advanced packaging fabs there, covering AI, heterogeneous packaging, silicon photonics, high-speed broadband, quantum technology and net zero.

If the plan is realized, TSMC's packaging footprint in Chiayi would rise to ten fabs. That would make the site one of the largest advanced packaging clusters in the world, and it would sit alongside — not replace — the existing Zhunan and Tainan sites.

Zhunan AP6, which opened in June 2023, was TSMC's first fully automated facility integrating 3D Fabric front-end and back-end processes plus testing. It is the largest CoWoS base in Taiwan and carries key orders from NVIDIA and AMD. Tainan AP8, converted from an Innolux fab, is planned to be larger than AP6 and is expected to host CoWoS first, with fan-out (InFO) and 3D IC lines potentially following. Taiwanese media have also reported plans for four more advanced packaging fabs in Tainan.

The geography tells you what the strategy is. Wafer fabs are moving to the United States for policy and customer reasons. Packaging is staying in Taiwan, where the ecosystem, engineering depth and cluster density are hardest to replicate.

10. The demand case

Expansion plans are only credible if orders support them, and the order data in the report is unusually specific.

Major customers — Apple, NVIDIA, AMD, Qualcomm and MediaTek — have reportedly increased orders by 10% to 20%. TSMC is accelerating 2nm capacity, with monthly output potentially reaching 120,000 wafers by year-end, above earlier market estimates of 90,000 to 100,000. Senior vice president Y.J. Hou said at the North America Technology Forum that five 2nm fabs are ramping simultaneously this year, the first time in the company's history.

The process roadmap compounds the effect. TSMC expects N2 and A16 capacity to grow at a 70% compound annual rate from 2026 to 2028, while N3 and N5 capacity grows at 25% from 2022 to 2027. First-year wafer output for N2 is expected to be 45% higher than N3 at the same point, reflecting closer collaboration between R&D and manufacturing.

Demand from AI is the driver. Between 2022 and 2026, customer demand for AI accelerators grew 11 times, and demand for large-die wafers grew six times. Large dies are exactly the products that consume the most packaging capacity, which is why CoWoS and SoIC expansion runs in parallel with wafer expansion rather than after it.

What the order increase really means

A 10% to 20% order increase from five major customers sounds modest. In leading-edge manufacturing it is not, because those customers are already allocated. An incremental order of that size has to come from capacity that is either newly qualified or diverted from someone else, and diversion is rare when contracts include volume commitments.

That is why TSMC is pushing 2nm output toward 120,000 wafers per month and ramping five 2nm fabs at once. The company is not adding capacity for a hypothetical market; it is trying to catch up with orders it has already taken. The 45% higher first-year wafer output for N2 versus N3 is a measure of how much faster the learning curve is being driven.

For buyers, the practical implication is that allocation conversations in 2027 will be decided by 2028 packaging capacity, not by 2022 wafer contracts. The companies that locked packaging capacity early will get the accelerators; the ones that locked wafers only will find themselves waiting for a slot.

11. What this means for buyers

Capacity allocation is a packaging question. If your product needs CoWoS or SoIC, the binding constraint is not wafer starts. Track packaging qualification timelines, not fab groundbreakings.

Watch the Arizona packaging lines. AP1 (SoIC) and AP2 (CoPoS) determine whether U.S.-made wafers can be packaged in the United States. Until they run, U.S. capacity still depends on Asian packaging for the most advanced products.

Expect substrate and HBM coupling. A 14x-reticle CoWoS package with 20 HBM stacks consumes far more substrate area and memory than today's parts. Substrate and HBM supply will constrain AI accelerator output as much as packaging does.

Do not treat the Texas report as capacity. Even if approved, a six-fab site would take years to contribute. Plan 2027–2029 allocations around Arizona and Taiwan, and treat Texas as 2030+ optionality.

Price in the cost gap. U.S.-made leading-edge wafers carry higher depreciation and labor costs. If your contract assumes Taiwan cost structures, renegotiate the assumption before the allocation conversation.

Diversify at the platform level. For commodity parts around the SoC, dual sourcing is straightforward. For the SoC itself, the realistic hedge is a second platform generation, not a second vendor.

12. Scenarios

The scenario that deserves the most attention is the last one. Packaging decisions are cheaper, faster and closer to revenue than fab decisions. If TSMC has to choose where to put marginal capital in a given year, packaging wins on payback — which is why Chiayi may matter more to 2027 supply than any Texas announcement.

13. The two questions that actually matter

The first is whether advanced process development stays in Taiwan. Every official statement says it will. But development follows volume, and volume is shifting. The A16 and subsequent nodes will be defined by the engineers who debug them at scale, and the scale is increasingly American.

The second is when the U.S. cost curve converges. TSMC can absorb a two-to-five-times construction premium at leading-edge prices. It cannot absorb it indefinitely across ten fabs, two packaging plants and a second cluster without either raising prices or accepting lower returns. Convergence depends on local supplier maturity, workforce productivity and utilization — none of which arrive on a schedule.

Neither question is answered by counting fabs. Both are answered by watching where the first silicon of each new node is debugged, and what TSMC says about gross margin by geography.

There is a third question that rarely gets asked: what would make the Texas plan unnecessary? If Arizona's packaging lines come online on schedule, if 2nm utilization stays high enough to justify ten fabs in one place, and if the cost gap narrows faster than expected, a second cluster becomes optional rather than strategic. None of those conditions is under TSMC's sole control, which is why the plan is being discussed publicly before it is decided privately.

14. Timeline

15. FAQ

Is the Texas plan confirmed?

No. It was reported by Taiwan's Economic Daily citing equipment-industry sources. TSMC has not confirmed it, and officials say any decision belongs to the board.

Would it replace Arizona?

No. The reported plan is for a second cluster in addition to Arizona, which is committed at $265 billion.

Why six fabs?

The number reflects what a viable cluster needs: enough volume to justify shared utilities, supplier presence and workforce investment. At 20,000–25,000 wafers per month each, six fabs imply 120,000–150,000 wafers per month.

Does this mean advanced R&D moves to the U.S.?

Officials say no, and TSMC has consistently said the most advanced development stays in Taiwan. Manufacturing expansion and development location are separate decisions — for now.

What is CoPoS?

A panel-level packaging technology positioned between wafer-level CoWoS and future large-format packaging. TSMC plans it for AP2 in Arizona and possibly P4 or P5 in Chiayi.

What is WMCM?

Wafer-level multi-chip module, a packaging approach that integrates multiple dies at wafer level. Chiayi P1 is described as an Apple-exclusive WMCM line.

Why does packaging capacity matter more than wafer capacity?

AI accelerators are limited by the number of packages that can be assembled and tested, not by the number of wafers started. A wafer that cannot be packaged cannot ship. With 20 to 24 HBM stacks per package planned, packaging also sets how much memory each accelerator consumes.

What should distributors watch?

CoWoS lead times, Arizona AP1/AP2 progress, and any board announcement about Texas. The first two affect 2027 supply; the third affects 2030.

16. Glossary

• CoWoS — chip-on-wafer-on-substrate; TSMC's 2.5D packaging platform for logic and HBM.
• SoIC — system on integrated chips; TSMC's 3D stacking technology.
• CoPoS — chip-on-panel-on-substrate; a panel-level packaging approach.
• WMCM — wafer-level multi-chip module.
• Reticle — the exposure field of a lithography tool; package size is often described as a multiple of it.
• HBM — high-bandwidth memory, stacked DRAM used alongside AI accelerators.
• InFO — integrated fan-out packaging.
• N2 / A16 — TSMC process nodes; A16 follows N2.
• Wafers per month (wpm) — the standard capacity unit for a fab.

17. Sources

• TSMC investor relations and quarterly earnings materials: investors.tsmc.com
• TSMC newsroom and technology symposium disclosures: tsmc.com
• Taiwan Ministry of Economic Affairs / park administration announcements on Chiayi: moea.gov.tw
• Economic Daily (Taiwan) report, September 30, 2026

18. Related reading

For how packaging and licensing disputes move through the supply chain, see our analysis of the Qualcomm–Arm royalty trial and our review of the four signals reshaping the 2026 chip supply chain.