TVS Selection: Standoff, Clamp, Current, Capacitance

A TVS is chosen by four numbers and the order matters. Get the standoff wrong and it conducts in normal operation; get the clamp wrong and it protects nothing.

Quick Answer

VRWM (standoff) must be above the maximum continuous voltage, including tolerance and ripple.
VC (clamp) at your surge current must be below the protected IC's absolute maximum.
IPP must exceed the surge current for the standard you are testing to.
Capacitance must fit the signal: hundreds of pF on power, under a few pF on high-speed data.

1. The four numbers

TVS voltage-current curve showing standoff, breakdown and clamping — Figure 1 — Below VRWM the part leaks microamps; above breakdown it conducts and clamps.

Parameter	Rule	Failure if wrong
VRWM	Above rail max, with margin	Leaks or conducts in normal use
VBR	Above VRWM; sets conduction point	Clamps too early or too late
VC at IPP	Below IC absolute maximum	IC dies with the TVS intact
C	Fits the signal budget	Eye closure on high-speed links

2. Clamp voltage is a curve, not a number

Clamping voltage versus peak current for three TVS types — Figure 2 — The datasheet value is measured at one current; at higher current it rises with the dynamic resistance.

VCL(I) ~ VBR + Rd x I

Example: 8 kV ESD contact -> about 24 A
VBR 6.1 V, Rd 1 ohm -> VCL ~ 30 V at the part

That is why "clamping voltage 12 V" on a datasheet does not mean the IC sees 12 V during an 8 kV strike. The IC sees the clamp plus the inductive drop of the trace between them — which is the argument for placing the TVS at the connector.

Dynamic resistance is the useful figure for extrapolation. A part with 0.5 Ω adds 12 V at 24 A; a part with 1.5 Ω adds 36 V. Two parts with the same headline clamp can behave very differently under a real strike.

3. Pick the standard first

IEC 61000-4-2 ESD, 61000-4-4 EFT and 61000-4-5 surge test levels — Figure 3 — ESD, EFT and surge stress a part differently; one TVS rarely covers all three.

Test	Typical level	TVS characteristic
ESD (61000-4-2)	±8 kV contact	Fast response, low capacitance
EFT (61000-4-4)	±2 kV bursts	Repeated pulses, thermal
Surge (61000-4-5)	0.5–4 kV	High energy, larger package

4. A worked selection

5 V rail with ±5 % tolerance and 100 mV ripple: maximum continuous is about 5.35 V. Choose a part with VRWM at least 5.5–6 V. The protected IC has an absolute maximum of 6.5 V; the TVS must clamp below that at the expected surge current, which for ESD means checking the curve at 20–30 A, not at 1 A.

That combination is often impossible with a small SMD TVS at 5 V: the clamp at 24 A may be 15–20 V, far above the 6.5 V absolute maximum. The realistic answer is that the TVS limits the energy and the IC's own ESD structure handles the residual — which is why system-level testing matters more than the datasheet arithmetic.

A second example, 24 V industrial input: maximum continuous maybe 26.4 V with tolerance. Choose VRWM 26–28 V, and check the clamp at the surge current for your test level — a 4 kV surge can push tens of amps, and the resulting clamp may exceed the downstream regulator's 40 V rating. That is the case for a two-stage design: a high-energy part at the connector plus a lower-clamp part after a series impedance.

Rail	Typical VRWM	Watch
3.3 V	3.6–5 V	Low clamp vs 3.3 V IC abs max
5 V	5.5–6.5 V	Tolerance + ripple can reach VRWM
12 V	13–15 V	Load dump if automotive
24 V	26–30 V	Clamp vs regulator rating

5. TVS versus the alternatives

Comparison of TVS, varistor, zener and polymer ESD suppressors — Figure 4 — Different jobs: energy, precision, capacitance, size.

A varistor absorbs more energy but is slower and capacitive; a zener clamps precisely but handles little energy; a polymer suppressor is small and fast but limited. For a power input, a TVS plus a fuse or eFuse is the usual combination; for high-speed data, a low-capacitance array.

6. Layout

TVS placement with a short ground return at the connector — Figure 5 — Short, wide ground; the clamp only protects what is downstream.

Place the TVS at the connector, before any series element.
Ground with short, wide copper and multiple vias — not a thin trace.
Keep the protected trace short; every millimetre adds inductance.
Do not route the surge path through the IC's ground.

For the pin-level layout of a USB port, the USBLC6 ESD guide walks through the same placement with numbers.

6b. Selection checklist

Step	Pass
VRWM	Above rail maximum with margin
Clamp at test current	Below IC absolute maximum
Peak pulse power	Above the standard's level
Capacitance	Within the signal budget
Leakage	Below the system's standby allowance
Layout	At connector, short ground

7. FAQ

Can one TVS protect both power and data?

Rarely well. Power needs energy handling; data needs low capacitance. Use an array for data and a separate part for the rail.

Why does my 5 V TVS conduct at 5 V?

VRWM is a standoff, not a clamp. A part rated 5 V may start conducting near 6 V, and a rail with tolerance can reach it. Choose the next voltage up.

Is a lower clamp always better?

Not if it costs capacitance or energy handling. Match the clamp to the IC's absolute maximum, not to the lowest number available.

Do I need a fuse with a TVS?

For a power input, usually yes. The TVS clamps the transient; the fuse or eFuse limits the follow-on current.

How do I test it?

System-level IEC tests at the connector, with the cable and enclosure. Device-level ratings do not guarantee system results.

What is peak pulse power?

It is the short-duration power the part can absorb, usually specified with an 8/20 µs waveform. It is not the same as continuous dissipation; read the derating curve.

Does capacitance matter on a slow signal?

Only if the source impedance is high. On a 100 kHz I2C bus with 4.7 kΩ pull-ups, a few hundred pF is already visible.

8. Sources

IEC 61000-4-2 / -4-4 / -4-5 — ESD, EFT and surge test standards.
TVS datasheets — VRWM, VBR, VC at IPP, capacitance, peak pulse power.
Application notes on TVS selection and layout (Littelfuse, Bourns, ON Semiconductor).