I2C Pull-Up Resistors: Fix 100 kHz and 400 kHz Errors
I2C pull-up resistors need to satisfy both a rise-time limit and a low-level drive requirement.
A sensor responds on a short cable, then disappears when a second module is connected. A prototype works at 100 kHz but reports errors at 400 kHz. Someone recommends replacing every resistor with 4.7 kOhm. That may improve the circuit, but it does not explain the original failure or establish a reliable production design.
This guide turns that familiar troubleshooting question into a calculation and a measurement plan. It covers ordinary resistor-pulled Standard-mode and Fast-mode buses, including common ESP32 and STM32 projects. The numerical examples are calculated scenarios, not oscilloscope measurements or guarantees for a particular board. Device data sheets, voltage domains and the assembled bus still decide whether a value is acceptable.
1. Why the bus needs pull-up resistors
In a conventional open-drain I2C connection, a participant pulls a signal low or releases it. The resistor brings a released signal back towards the pull-up supply. It therefore forms part of the electrical interface rather than an optional software convenience. SDA and SCL need their own pull-up paths, and the devices need a valid common reference.
A large resistance draws less current while the line is low, but charges the bus capacitance more slowly. A small resistance raises the line faster, but asks every participating output to sink more current. A value can fail on either side of that trade-off. Replacing a resistor based only on whether a scanner finds a device misses this electrical constraint.
Separate the bus pull-ups from optional series damping resistors and from resistors on an unrelated interrupt output. Their locations and purposes differ. Start with the actual schematic and fitted components, including the ones hidden on breakout boards.
2. Why 100 kHz can work while 400 kHz fails
The nominal clock frequency is not the same measurement as the signal's rise time. After an output releases the line, resistance and capacitance determine how quickly its voltage crosses the receiving thresholds. Shortening the clock period does not automatically make that charging process faster.
The NXP I2C specification gives a maximum rise time of 1000 ns for Standard-mode and 300 ns for Fast-mode. Its RC sizing method measures the transition between 30% and 70% of the pull-up voltage. A scope's default 10% to 90% measurement answers a different question, so configure the thresholds or calculate the correct interval before comparing results.
| Bus mode | Maximum clock | Maximum rise time | What the check does not prove |
|---|---|---|---|
| Standard-mode | 100 kHz | 1000 ns | Other timing, voltage and protocol requirements still apply |
| Fast-mode | 400 kHz | 300 ns | Every connected device must support the selected mode |
| This guide's calculations | 100 kHz or 400 kHz | 30% to 70% thresholds | Not a Fast-mode Plus or High-speed design approval |
Slowing the clock is a useful diagnostic experiment. If it helps, investigate the waveform and timing budget rather than declaring the fault solved. Address errors, power sequencing and device-specific transaction requirements can remain even when the edges look better.
3. Calculate the minimum resistance from low-level drive
The lower resistance bound comes from the output's ability to hold a valid low level. Use the specified sink-current condition and maximum low-level output voltage for the relevant device and operating conditions. Do not substitute a GPIO absolute-maximum current or a whole-chip current rating for that electrical guarantee.
Rp(min) = (Vpullup - VOL(max)) / IOL
For an illustrative 3.3 V bus, assume every output that may pull a line low is specified for 0.4 V maximum at 3 mA. The calculation gives approximately 967 Ohm. A smaller resistance would demand more than the assumed current at that low-level voltage. This example does not assert that every ESP32, STM32, sensor or buffer has identical specifications.
Check the weakest applicable driver, including a target that acknowledges on SDA or stretches SCL when that feature is used. A controller with a strong output cannot compensate for another device that cannot meet its low-level requirement. Supply tolerance also matters: evaluate the high end of the pull-up rail when checking the strongest pull-up current.
4. Calculate the maximum resistance from capacitance
For the simple RC model, the rise-time relationship gives the upper resistance bound. TI's application note SLVA689A presents the same sizing approach as the NXP specification. The capacitance belongs to one bus line and includes device pins, traces, connectors, wiring and measurement loading; it is not just the capacitance printed for one sensor.
tr = 0.8473 x Rp x Cb
Rp(max) = tr(max) / (0.8473 x Cb)
With an assumed 200 pF line capacitance, the calculated upper bound is about 5.90 kOhm at 100 kHz and 1.77 kOhm at 400 kHz. Combine those results with the previous 967 Ohm lower bound. There is a nominal window in both cases, but it becomes much narrower at the faster bus speed.
Use consistent units: seconds, Ohm and farads in the formula. A spreadsheet that mixes pF with farads can produce a plausible-looking number with an enormous error. Write the units alongside the inputs and check one result independently before selecting parts.
5. Compare 4.7 kOhm, 2.2 kOhm and 1.5 kOhm
Keep the same 200 pF assumption and calculate the rise time for three familiar resistor values. This isolates the effect of resistance; it does not represent three measured boards. The table compares only the stated RC rise-time limit and the earlier nominal low-level bound.
| Pull-up resistance | Calculated rise time | 100 kHz rise-time limit | 400 kHz rise-time limit |
|---|---|---|---|
| 4.7 kOhm | 796 ns | Within 1000 ns | Exceeds 300 ns |
| 2.2 kOhm | 373 ns | Within 1000 ns | Exceeds 300 ns |
| 1.5 kOhm | 254 ns | Within 1000 ns | Within 300 ns; check tolerances and VOL |
The result explains why changing 4.7 kOhm to 2.2 kOhm may improve a bus without making this particular 400 kHz example compliant. The 1.5 kOhm value is a candidate under the assumptions, not a universal recommendation. Recalculate when the voltage, device drive conditions or total capacitance changes.
Do not choose a resistor exactly at a calculated limit. A nominal pass that disappears with a longer cable or a different component lot is an unfinished margin assessment. Keep the calculations attached to the specific board configuration used for approval.
6. Count the pull-ups already fitted to modules
Several modules can each contain a perfectly reasonable pull-up and still create an unsuitable combined load. Resistors connected from the same signal to the same rail act in parallel. Calculate SDA and SCL separately because their fitted networks need not be identical.
1 / Reffective = 1 / R1 + 1 / R2 + ...
Two 4.7 kOhm resistors on one line produce 2.35 kOhm. Four produce 1.175 kOhm. Five produce 940 Ohm, below the illustrative 967 Ohm minimum from our 3.3 V example. Adding modules may simultaneously increase capacitance and strengthen the pull-up, so the resulting behavior is not explained by device count alone.
Inspect module schematics and fitted components before changing jumpers or removing resistors. Keep the final population documented so a replacement module does not silently alter the network. A resistance measurement with power off can help, but other semiconductor paths may affect the reading; interpret it with the schematic.
7. Check voltage domains before changing resistance
The pull-up rail determines the released high level. A 5 V pull-up does not become safe for a 3.3 V-only input merely because the resistor limits current. Check pin-voltage limits, input thresholds, powered-off behavior and any permitted injection current in the exact device documentation.
Open-drain operation helps devices share a line, but it is not automatic voltage-level translation. A dedicated translator or qualified discrete circuit may be needed. A buffered or translated bus can have separate segments, different capacitances, offsets and pull-up requirements. Do not apply one lumped RC calculation across a device whose architecture changes the electrical model.
Power sequencing also deserves a check. A target that is off while the bus remains powered can clamp a line or receive current through protection structures, depending on its design. Test the intended sequence and consult its powered-off specifications. Increasing drive strength or repeatedly restarting firmware is not a substitute for resolving an incompatible electrical connection.
8. Treat internal pull-ups as a documented design choice
Internal pull-ups are convenient, but their resistance and variation may not suit the bus capacitance and speed. Enabling a configuration flag is not evidence that the assembled interface meets its rise-time requirement. Check the specified range and include it when calculating any parallel combination with external resistors.
Espressif's ESP32 I2C documentation recommends suitable external pull-ups and notes that internal pull-ups are not strong enough for higher-speed operation. It also identifies pull-up checks as part of diagnosing a probe timeout. That is useful troubleshooting guidance, not a statement that every timeout has the same cause.
For an STM32 or another MCU, use the specific part's electrical data, reference manual and applicable errata. Family names do not establish pin characteristics, peripheral behavior or the board's fitted resistors. Record the software configuration together with the hardware values so a firmware update does not unknowingly change the effective bus network.
9. Measure the edge where the receiver sees it
Use an oscilloscope to inspect the analog waveform at relevant endpoints, with a suitable probe and a short ground connection. Account for probe loading when interpreting the result. A logic analyzer can reveal addresses, acknowledgements and transaction ordering, but a clean decode is not a complete analog margin measurement.
Measure SDA and SCL rise times using the required threshold convention, and inspect the low level when different devices are driving. Look for ringing, unexpected dips and timing differences between the controller and distant targets. A single screenshot from the easiest transaction does not cover every operating condition.
Repeat the relevant checks with the final harness, all intended modules, supply limits and required temperature range. Preserve the bus speed, resistor population, probe setup and firmware version with the capture. These records make a later component or module change reviewable instead of relying on someone's memory that the old prototype worked.
10. Separate electrical failures from protocol mistakes
A missing acknowledgement can come from the wrong address, an unpowered target, a transaction the device does not support or an electrical problem. Read the device's address convention and library expectations together. Some documentation presents address bits differently from the API argument; copying a number without checking that convention can create a convincing false diagnosis.
| Observed symptom | First useful check | Avoid assuming |
|---|---|---|
| Works slowly, fails at higher speed | Measure rise time, timing margins and supported mode | Every failure is solved by 2.2 kOhm |
| No acknowledgement at any speed | Power, address convention, pin mapping and waveform | The IC must be defective |
| Fails after adding a module | Parallel pull-ups, capacitance, addresses and rail compatibility | More pull-ups always help |
| SDA or SCL remains low | Identify the held line and inspect state, power and reset | A scanner or an arbitrary pulse loop will recover it |
Address collisions are another reason a bus can fail only after expansion. Isolate devices in a controlled test and compare their configured addresses. Keep one variable changing at a time; simultaneously replacing resistors, updating firmware and changing the cable makes a successful result difficult to explain or reproduce.
11. If there is no resistance window, change the design
Consider 400 pF at 400 kHz with the same illustrative 3.3 V, 0.4 V and 3 mA assumptions. The calculated maximum resistance is about 885 Ohm, while the minimum remains about 967 Ohm. No passive resistor satisfies both nominal constraints in that model. Picking the midpoint does not solve the contradiction.
Possible design changes include reducing capacitance, revisiting the supported speed, selecting suitably specified drivers or using a qualified buffer architecture. Each option has its own constraints. A stronger driver must be supported by every relevant low-driving participant, and a buffer needs its own voltage, timing and topology review.
A stuck bus is a separate state-recovery problem. NXP describes nine clock pulses for SDA held low, with reset or power cycling if recovery fails; SCL held low requires a different recovery path. Apply the device and controller guidance without driving against a held line. TI's stuck-bus note also discusses false clock edges, interference and reset conditions. Recovery should accompany root-cause work, not hide repeated failures.
12. Specify a resistor, not just a familiar value
For release, document resistance, tolerance, package and any relevant voltage, power or temperature requirements. Check the low-resistance tolerance corner against sink capability and the high-resistance corner against rise time. Include supply variation and a justified maximum capacitance rather than using a room-temperature nominal estimate everywhere.
As a calculation example, 1.5 kOhm with a 5% resistance tolerance reaches 1.575 kOhm at its high end. At 220 pF, its modeled rise time is about 294 ns. That leaves little room below 300 ns; further uncounted capacitance can remove the margin. The example illustrates sensitivity, not an endorsed production value.
When purchasing a module or alternate IC, request the exact schematic revision, fitted pull-ups, voltage-domain information and ordering code. Confirm that the replacement preserves the approved interface requirements. A cheaper component that changes drive strength, pin behavior or the module resistor network needs engineering review before it becomes a purchasing substitution.
13. Frequently asked questions
Are 4.7 kOhm pull-ups always correct for I2C?
No. The acceptable resistance depends on the pull-up voltage, device sink capability, bus capacitance and timing requirements. In the stated 200 pF example, 4.7 kOhm produces about 796 ns rise time: within the Standard-mode rise-time limit, but above the Fast-mode limit. Other electrical and protocol checks still apply.
Does every sensor need its own pair of pull-ups?
Not on an ordinary shared bus segment. Existing pull-ups combine electrically, so adding a pair with every module can make the total resistance too small. Inventory the actual fitted network on each signal. Separate buffered or level-translated segments may require their own pull-ups according to the relevant device documentation.
Can I use internal pull-ups on an ESP32?
Do not assume they are sufficient. Espressif recommends appropriate external pull-ups for the bus and warns about internal pull-up strength at higher speeds. Assess the exact controller, board, loading and configuration, then measure the waveform. A successful single probe is not a complete timing or voltage qualification.
Will a smaller resistor fix a missing I2C device?
Only if the diagnosed problem is compatible with that change and the new resistance remains acceptable. A smaller value increases low-state current. It cannot correct an invalid address, an unpowered device, an unsupported transaction or an unsafe pull-up voltage. Inspect the analog waveform and configuration before replacing components.
Why does connecting an oscilloscope change the result?
A probe adds loading and its ground connection can affect the observed waveform. On a marginal bus, that can change behavior as well as the measurement. Use suitable probing, document the setup and consider its capacitance in the model. Compare observations carefully rather than assuming the instrument is electrically invisible.
What should procurement confirm for a replacement module?
Confirm the exact device and board revision, permitted signal voltage, fitted pull-up values and interface requirements. Keep the approved schematic and test conditions available to engineering. A matching connector or a generic I2C label does not establish electrical interchangeability or justify changing the production BOM without review.
14. Sources and related engineering guides
Primary sources checked on October 30, 2026:
- NXP UM10204 I2C specification, Revision 7.0
- TI SLVA689A I2C pull-up resistor calculation
- Espressif ESP32 I2C configuration and troubleshooting
- TI SCPA069 stuck-bus prevention and workarounds
Related Chip-seek reading:
- STM32F103C8T6 alternatives and qualification checks
- AMS1117-3.3 alternatives and power-rail selection
Cover photograph: Golonlutoj, MicroSTM32, CC BY-SA 3.0. Crop and editorial layout by Chip-seek under the same licence. The pictured STM32F103R6T6 illustrates real hardware; it is not the board used for the calculations or a stock claim.
