HDMI and DisplayPort: A Practical Introduction
Before a single pixel moves, the source has to know a display is there and what it can accept. That conversation runs on two slow wires, and it is where most "no signal" problems start.
Quick Answer
- HDMI: three data lanes plus a clock (TMDS), 100 Ω differential, plus DDC, HPD and +5 V.
- DisplayPort: 1–4 lanes, 100 Ω, AC-coupled with 100 nF, plus AUX and HPD.
- EDID is an I2C EEPROM the source reads over DDC (HDMI) or AUX (DP). No EDID, no picture.
- HPD tells the source a display is connected; without it, many sources never start.
1. HDMI: TMDS lanes
HDMI 2.0 carries 6 Gb/s per lane (18 Gb/s total) over TMDS, DC-coupled, 100 Ω differential. HDMI 2.1 switches to FRL: four lanes, up to 12 Gb/s each, 48 Gb/s total, with different coding and AC coupling on some implementations.
TMDS sends video as a continuous stream with a dedicated clock lane; FRL packets the data and embeds the clock. That is why a board designed for TMDS does not automatically support FRL at full rate — the PHY, the connector and the layout all have to be rated for it.
| Signal group | What it does | Failure symptom |
|---|---|---|
| TMDS / FRL lanes | Video and audio | Sparkles, dropouts, no video |
| DDC (I2C) | EDID read, HDCP | Wrong resolution, black screen |
| HPD | "Display connected" | Source never wakes the link |
| +5 V | Powers the EDID EEPROM | No EDID, so no picture |
| CEC | Remote control passthrough | Remote does not control the source |
2. DisplayPort: lanes and AC coupling
DisplayPort uses 1, 2 or 4 main-link lanes, 100 Ω differential, with 100 nF AC coupling in series on each line. DP 1.4 runs HBR3 at 8.1 Gb/s per lane (32.4 Gb/s total); DP 2.0 adds UHBR rates with 128b/132b coding.
Link training is the part HDMI does not have: the source and sink negotiate voltage swing, pre-emphasis and lane count until every lane is error-free. If training fails, the link falls back to fewer lanes or a lower rate — and the symptom is a lower resolution rather than a dead link.
| Aspect | HDMI 2.0 | DP 1.4 |
|---|---|---|
| Lanes | 3 data + clock | 1–4 |
| Rate per lane | 6 Gb/s | 8.1 Gb/s (HBR3) |
| Coupling | DC (TMDS) | AC, 100 nF |
| Discovery | DDC + HPD | AUX + HPD |
| Power pin | +5 V, 50 mA | 3.3 V, up to 500 mA |
3. The conversation before video
- The sink asserts HPD (a level, not a pulse on some devices).
- The source powers the DDC/AUX bus and reads EDID — 128-byte blocks with an extension count.
- The source parses the timing list and picks a mode the display accepts.
- For HDMI, HDCP authentication follows; for DP, link training runs per lane.
If EDID is missing or corrupt, many sources fall back to a safe mode or show nothing. A surprisingly common cause is unpowered +5 V on HDMI: the EEPROM is powered from the source, so a broken trace kills the read.
EDID is 128 bytes for the base block, with optional extension blocks (CEA-861 for HDMI). The base block contains the manufacturer ID, the preferred timing and a list of established timings; the extension carries the video formats, audio and HDMI-specific data. A display that only advertises 1080p will not give you 4K, no matter what the source can do.
When a design fails at 4K but works at 1080p, read the EDID and check two things: whether the 4K timing is present, and whether the HDMI 2.0 VSDB (vendor-specific data block) declares support for the higher rate.
4. Routing rules
- 100 Ω differential, from the connector's stackup, not from a guess.
- Match within each pair; keep pairs short and avoid vias.
- Continuous ground under the pairs; the connector area is where planes are cut.
- Keep the DDC/AUX and HPD lines away from the high-speed pairs, and protect every exposed pin with ESD.
- Check the PHY's maximum trace length; at 6–8 Gb/s the budget is short.
4b. Lane count versus resolution
| Link | Typical use |
|---|---|
| DP 2 lanes, HBR2 | 1440p at 60 Hz, 1080p high refresh |
| DP 4 lanes, HBR3 | 4K at 60 Hz, dual 1440p |
| HDMI 2.0 | 4K at 60 Hz (4:2:0 or 4:2:2) |
| HDMI 2.1 FRL | 4K high refresh, 8K |
5. Common mistakes
| Mistake | Symptom | Fix |
|---|---|---|
| HPD not connected | Source never detects the display | Wire it; verify the level |
| No +5 V on HDMI | EDID read fails | Check the source-side supply |
| EDID not programmed | Wrong mode or black screen | Program a valid 128-byte block |
| DP AC caps missing | Link training fails | 100 nF per line, close to TX |
| 90 Ω routing for 100 Ω pairs | Intermittent link at high rate | Re-route per stackup |
For the pair fundamentals that apply to both, see the USB 2.0 pair routing guide; for protection placement at the connector, the ESD layout guide.
6. FAQ
Why does my display show "no signal" with a known-good cable?
Check HPD and EDID first. Most "no signal" cases are the sideband, not the high-speed lanes.
Can I convert HDMI to DisplayPort with a cable?
Only with an active converter. The protocols and electrical rules are different; a passive cable will not work.
Does HDMI 2.1 need new cables?
For 48 Gb/s, yes: certified Ultra High Speed cables. Older cables may work at lower rates only.
Why is the resolution wrong?
The EDID timing list, or a fallback mode after a failed read. Read the EDID over DDC and compare with the display's capabilities.
What is HDCP?
Content protection negotiated over DDC/AUX. If authentication fails, the source may show a black screen with a message.
Why does my sink not wake the source?
HPD may be missing, inverted, or not driven to the right level. Measure it at the connector before changing anything else.
Is DP better than HDMI?
Neither is universally better. DP is common on monitors and supports more lanes; HDMI is common in consumer AV. Choose by the ecosystem, not by the spec sheet.
7. Sources
- HDMI Licensing Administrator, HDMI specification and compliance.
- VESA, DisplayPort standard.
- Texas Instruments, High-Speed Layout Guidelines (SLLA414).
- Vendor PHY and redriver datasheets — trace length, equalisation and AC coupling requirements.
Designing a display port?
Send the connector type, resolution and cable length. We will check the lane count, EDID plan and pair routing before you build.
