Buck Converter Layout: Hot Loop, Switch Node, and Copper

A switching regulator's efficiency is decided by the schematic; its temperature is decided by the layout. The hot loop sets the ringing, and the copper sets whether the heat has anywhere to go.

1. The hot loop is the layout

The high-side FET turns on and current flows from the input capacitor through the FET and back through the ground connection. That loop carries a pulsed current with nanosecond edges; every millimetre of it is inductance, and the energy in that inductance rings when the FET switches.

Practical rule: place the input capacitor within a few millimetres of the FET pair, put the ground return directly under the loop on the same layer if possible, and never route the loop through a via if a surface path exists.

Finding the loop is easy: put a finger on the schematic and trace the path the current takes when the high-side FET is on. It goes from the capacitor's positive terminal, through the FET, through the inductor, and returns through the low-side FET and the ground plane to the capacitor's negative terminal. That closed path is the loop; every part of it matters, including the return.

What a large loop actually does: the parasitic inductance resists the current step, the switch node overshoots, and the energy ends up as ringing that couples into the ground plane and the feedback trace. The converter still regulates, which is why the problem hides until EMC or a field failure.

The loop area is what couples to the rest of the board. A few mm² is a tight layout; tens of mm² is a loop that listens to the switch node and radiates it.

2. The input capacitor: value is not enough

Irms = Iout x sqrt(D x (1 - D))

12 V -> 5 V, D = 0.42, Iout = 2 A:
Irms = 2 x sqrt(0.42 x 0.58) = 2 x 0.494 = 0.99 A

That current flows in the capacitor's ESR, and it is why a 10 µF ceramic can run warm even though the DC current through it is zero. Choose the capacitor for ripple current, not just capacitance, and check the DC-bias derating: a 10 µF X5R at 12 V may be 5 µF in circuit.

Worked example: 12 V to 5 V at 2 A, D = 0.42, 500 kHz. A 10 µF X7R 25 V part might be 6 µF at 12 V bias; with 0.99 A RMS the ripple is fine, but two 4.7 µF parts in parallel often beat one 10 µF because the ESR and ESL halve and the effective capacitance under bias is higher.

Place the small capacitor first, closest to the FETs; the bulk capacitor can be a few millimetres away. The order matters more than the total value.

3. The switch node: keep it small and quiet

The switch node is the copper between the FETs and the inductor. It swings between ground and Vin at the switching frequency, so it is both a noise source and a radiator. Keep the copper just large enough for the current, and keep everything sensitive away from it.

The node's capacitance is the sum of the FET output capacitance, the inductor's parasitic capacitance and the copper itself. Every extra mm² adds capacitance, and that capacitance is charged and discharged at Vin every cycle — loss that does not appear in the conduction equation.

• No feedback trace, no enable trace, no current-sense trace near the node.
• No test points on the node unless needed; a 2 mm pad is an antenna.
• If ringing exceeds the FET rating, add an RC snubber across the low-side FET, or slow the high-side turn-on with a gate resistor.

4. Ground: one plane, one return

Use a solid ground plane under the converter. The power ground and the analog ground meet at one point — usually the IC's ground pad — and the feedback divider is referenced to that point, not to the switching return.

A split ground with a long bridge is worse than one plane: the return current finds the bridge, and the bridge is an inductor. If the board has analog and digital sections, partition by placement, not by cutting the plane.

If the controller has separate AGND and PGND pins, connect them at one point under the IC and keep the feedback divider referenced to AGND. Do not rely on two return paths — the switching current will find both, and the quieter one will no longer be quiet.

5. Thermal: the loss budget first

A 0.6 W total in a DFN 3×3 with θJA of 45 °C/W is a 27 K rise — comfortable. The same 0.6 W in a package with 100 °C/W is a 60 K rise, and in a sealed box at 60 °C it is at the limit. The heat has to leave through the pad, the vias and the copper, so the layout is the thermal design.

A typical efficiency target for a 12 V to 5 V, 2 A design at 500 kHz is 92–95 %. If the measured number is 88 %, the first suspects are switching loss (too slow a gate drive), inductor DCR (a small case chosen for size), and the input capacitor (a low-value part that lets the rail sag).

5b. Thermal path, in order

Do the free steps first. Most buck layouts that run hot are missing vias or copper, not a heatsink.

6. Feedback and control

Route the feedback divider from the output capacitor's positive terminal, not from the inductor. The trace should be short, away from the switch node and the inductor, and referenced to the analog ground at the IC.

For a converter with an external compensation network, place it next to the IC and keep the sensitive node small. A long trace on the compensation pin picks up the switch node and turns a stable loop into a jittery one.

7. Measuring the result

1. Switch node with a short ground and a low-capacitance probe: check overshoot and ringing at the worst-case load.

Scope the switch node with a very short ground lead. A 10 cm clip lead adds enough inductance to invent ringing that is not there, and then the fix is chasing a measurement artifact.

2. Input ripple across the capacitor: it tells you whether the loop and the capacitor are doing their job.
3. Efficiency at 25 %, 50 %, 100 % load: a curve, not a single point.
4. Thermal at full load for 30 minutes in the enclosure; measure the inductor and the FET, not just the IC.
5. Load step: check recovery and overshoot with the real output capacitor.

This closes the thermal cluster: the AMS1117 guide covers linear dissipation, the LM317 guide covers heatsink sizing, and the TP4056 guide covers a linear charger. The buck is the case where the loss is small enough that layout, not the package, decides the temperature.

8. FAQ

Can I use a two-layer board for a buck converter?

Yes at low current and low frequency, but the hot loop must be on one layer with a direct return. A four-layer board with a solid ground plane is much more forgiving.

Is a larger inductor always better?

No. Larger inductance lowers ripple but raises DCR and size, and the core loss changes with the material. Optimise for the switching frequency you actually use.

Do I need a snubber?

Only if the ringing exceeds the FET rating or radiates. Measure first; a snubber costs efficiency and board space.

Why is the input capacitor hotter than expected?

Because it carries the ripple current, not the DC current. Check the RMS rating and the DC-bias derating, not just the capacitance.

Where should the thermal vias go?

Under the FET or IC thermal pad, connected to a copper area on the other side. Four to nine vias of 0.3 mm is a typical start.

Does layout affect efficiency or only temperature?

How do I know the loop is small enough?

Look at the layout: the input capacitor should touch the FET pair. If there is a via or more than a couple of millimetres of trace between them, the loop is bigger than it needs to be.

Why does my converter get hot at light load?

At light load the switching and gate losses dominate, and they do not fall with current. If the design is optimised for full load, light-load efficiency suffers; some controllers offer a pulse-skipping mode to address it.

Should the inductor be shielded?

Shielded parts reduce the field that couples into feedback and signal traces. For a converter near analog circuitry, the small cost is usually worth it.

Mostly temperature and noise, but loop inductance also increases switching loss. A poor layout can cost a few percent of efficiency at high frequency.

9. Sources

• Texas Instruments, AN-1149: Layout Guidelines for Switching Power Supplies — hot loop, ground and feedback routing.
• Texas Instruments, High-Speed Layout Guidelines (SLLA414) — return path and via practice.
• Vendor buck converter datasheets — thermal pad dimensions, θJA and recommended land patterns.