USB 2.0 Differential Pair Routing: Impedance, Skew, and Return Path
At 480 Mb/s one bit is 2.08 ns. Everything that matters on a USB 2.0 board follows from that number: 90 Ω impedance, matched lengths, and a return path that never has to detour.
Quick Answer
- Impedance: 90 Ω differential, ±15 % (76.5–103.5 Ω). Ask the fabricator for the stackup before routing.
- Skew: keep the pair within 50 mil (1.27 mm), which is about 8.5 ps — 0.4 % of a bit.
- Return path: continuous ground under the pair. A split forces the return current around the gap and ruins the impedance.
- Rules of thumb: under ~100 mm of trace, at most two vias, no stubs, ESD at the connector.
1. What 480 Mb/s actually requires
| Parameter | Value | Why it matters |
|---|---|---|
| Bit period (UI) | 2.08 ns | Everything is measured against it |
| Differential impedance | 90 Ω ±15 % | Reflections show up as eye closure |
| Intra-pair skew | ≤ 50 mil (1.27 mm) | Common-mode conversion and jitter |
| Trace length (guideline) | ≤ ~100 mm | Attenuation and jitter budget |
| Vias per pair | ≤ 2 (guideline) | Each via is an impedance discontinuity |
| Cable | ≤ 5 m for HS | Beyond that, no layout fixes it |
These are the numbers from the USB 2.0 specification and the long-standing high-speed layout guidance from Intel and silicon vendors. The exact limits for a given PHY are in its datasheet or layout checklist, which always wins over general advice.
Why differential in the first place: the receiver looks at the difference between the two lines, so noise coupled equally into both cancels. That is also why the pair must be routed together — separation breaks the symmetry the cancellation depends on, and the noise stops being common-mode.
2. Impedance starts with the stackup
You cannot route 90 Ω by eye. Ask the PCB fabricator for a controlled-impedance stackup with the target marked, then use the width and gap they calculate for that stackup. The same geometry on a different dielectric thickness is a different impedance.
Two practical points. First, the ±15 % tolerance is a manufacturing tolerance — routing the pair at 80 Ω "because it is easier" is outside it. Second, impedance is measured on the finished board with a TDR coupon; if the fabricator cannot provide a coupon, the number is a hope, not a specification.
What actually sets the impedance: the dielectric thickness to the reference plane, the trace width, the gap between the two traces, and the copper thickness. A common starting point on 0.1 mm prepreg is 0.15 mm trace and 0.15 mm gap, but the fabricator's calculator is the authority — every stackup is different, and a 0.05 mm change in dielectric can move the impedance by several ohms.
If the board has an impedance coupon, test it before assembly. A batch that came out at 82 Ω will still enumerate, and it will fail the eye mask with the longest cable — which is the most expensive time to discover the problem.
3. Length matching: 50 mil is not arbitrary
Delay on FR-4: about 6.7 ps per mm 50 mil = 1.27 mm -> 8.5 ps One bit at 480 Mb/s = 2.08 ns -> 0.4 %
Match within a pair, not between pairs. The two pairs (D+ and D−) are one differential pair, not two independent signals: the requirement is that their lengths are equal, not that they follow the same path as another pair.
It is worth being precise about terms: D+ and D− form one differential pair. There is no second pair in USB 2.0 (SuperSpeed has two more). So the matching requirement is intra-pair only, which is why routing both lines together and keeping their lengths equal is sufficient.
The pair should also stay close together. Separating the two traces to route around an obstacle changes the differential impedance and the coupling; it is better to move both traces together, even if the detour is longer.
When you must add length, add it in the same place on both traces, with the same number of bends. A single 45° jog on one trace and three on the other keeps the length equal but creates a local impedance difference — acceptable at 50 mil, not at 500 mil.
4. The return path is the other half of the pair
High-speed current returns on the plane directly under the trace. If that plane has a slot, the return current has to go around it, and the loop area — and therefore the inductance — increases. The symptom is not "the pair is broken", it is "the eye is smaller than it should be".
If a plane change is unavoidable, add a stitching capacitor near the via (typically 100 nF) so the return current has a high-frequency path. Better: do not change the reference plane at all for a 480 Mb/s pair.
5. Vias, stubs and the ESD part
Vias add capacitance and, if unbackdrilled, a stub that resonates. For USB 2.0 the practical guideline is at most two vias per pair, matched in number on both lines, with the return via placed close to the signal vias.
A via stub is the unused portion of the barrel below the layer where the signal enters. On a 1.6 mm board, a via from L1 to L2 leaves about 1.4 mm of stub, which resonates in the high hundreds of megahertz — below the USB 2.0 band, which is why USB 2.0 tolerates vias better than 5 Gb/s does. On thicker boards or at higher rates, backdrilling is the fix.
The ESD part belongs at the connector, and its placement is covered in the USBLC6 layout guide: place it within a few millimetres of the port, route the signal through it (flow-through), and connect its ground to the plane with short vias. A common-mode choke, if fitted, goes after the ESD part, not between the connector and the protection.
6. Spacing and crosstalk
Keep other signals at least 3× the trace width away from the pair (centre-to-centre), and never run a switching node or a clock parallel to it. Differential pairs reject common-mode noise, but they do not reject a nearby aggressor that couples differently into each line.
In numbers: at 3W spacing, coupling into a neighbouring trace is typically a few percent; at 1W it can exceed 10 %. That is the difference between an eye with margin and one that closes when the neighbouring bus becomes active.
Cross the pair at 90° if you must cross another trace. Perpendicular crossing minimises the coupled length, and it is one of the few layout changes that costs nothing.
6b. Speed modes change the rules
| Mode | Rate | Routing priority |
|---|---|---|
| Low / Full speed | 1.5 / 12 Mb/s | Short traces, 90 Ω helpful but forgiving |
| High speed | 480 Mb/s | 90 Ω, 50 mil skew, continuous return |
| SuperSpeed | 5 / 10 Gb/s | 85 Ω, tighter loss and via budget |
A board designed for full speed will often enumerate at high speed by accident and then fail on a long cable. That is not a bonus; it is an unqualified margin. If the product can run HS, design for HS.
7. What breaks a link, in practice
| Symptom | Likely cause | Check |
|---|---|---|
| Enumerates at full speed only | HS handshake failing: impedance or skew | TDR on the pair; length match |
| Works with a short cable, fails with 2 m | Eye margin already consumed | Eye diagram at the connector |
| Drops under Wi-Fi or motor load | Crosstalk or ground bounce | Spacing, return path, shield bond |
| Fails ESD but works otherwise | Protection placement or ground | Distance to connector, via count |
| Intermittent on one board batch | Stackup or fabrication variation | TDR coupon from both batches |
7b. A representative failure
A product enumerates at high speed on the bench, drops to full speed when a 2 m cable is fitted, and works again with a 0.5 m cable. The pair is 85 mm long, matched, and runs past a DC-DC converter. TDR shows a 12 Ω dip about 60 mm along, and the layout shows the pair crossing a plane split under the converter.
The fix is not the cable and not the PHY settings: the return current was detouring around the split, adding inductance that closed the eye. Re-routing the pair 4 mm to stay over solid ground restores HS with the long cable.
8. Measuring it
- TDR on a test coupon or the finished pair: confirm 90 Ω ±15 % and look for dips at vias.
- Eye diagram at the far end with the longest supported cable: the mask is the specification, not "it works".
- Common-mode noise: probe both lines with a differential probe; asymmetry shows up as common-mode content.
- ESD: system-level test at the connector, with the cable attached.
- Temperature: repeat the eye at the hot and cold extremes; dielectric loss and driver strength both change.
If you do not have a TDR, an inexpensive alternative is a time-domain reflectometer mode on a fast scope with a step generator, or a vector network analyser sweep of S11/S21. For a prototype, the eye diagram with the worst-case cable is the acceptance test; the TDR tells you why it looks the way it does.
| Design check | Pass | If it fails |
|---|---|---|
| Impedance from stackup | 90 Ω ±15 % | Ask for a new stackup; do not guess |
| Intra-pair length | ≤ 50 mil | Add matching bends on the short line |
| Reference plane | Continuous under the whole run | Re-route or stitch the return |
| Vias | ≤ 2, matched, return via nearby | Re-route to reduce layer changes |
| ESD and choke order | Connector → ESD → choke → PHY | Swap; protection must see the port first |
The same return-path discipline appears in the SPI layout guide, the I2C timing guide and the crystal startup guide — different rates, same physics.
9. FAQ
Can I route USB 2.0 on a two-layer board?
Yes, but the pair must have a continuous ground reference directly underneath, with no gap under the run. Many two-layer boards work at full speed; the failures come from routing over a split or around a connector cutout.
Do I need 22 Ω series resistors?
For high speed, no — the PHY's driver is matched for 90 Ω. Series resistors appear in full-speed designs to tame edges; adding them to a HS pair degrades the eye.
How important is the ESD part's placement?
Very. The clamp only protects what is downstream of it, and the trace inductance between the connector and the part is added to the clamp. Place it within a few millimetres and route through it.
Does length matching apply between D+ and D− only?
Yes. It is one differential pair; matching to other signals is not required and can create unnecessary detours.
What about USB-C?
The same differential rules apply to D+/D−, and the connector adds CC and SBU pins that need their own protection. High-speed SuperSpeed pairs are a different problem with tighter limits.
Why does the board fail only with a long cable?
The cable adds loss and jitter; a design with a marginal eye passes with a 0.5 m cable and fails at 2 m. Test with the longest cable the product supports.
10. Sources
- USB Implementers Forum, USB 2.0 specification — signalling, impedance and eye requirements.
- Intel, High Speed USB Platform Design Guidelines — 90 Ω ±15 %, skew and via guidance.
- Texas Instruments, High-Speed Layout Guidelines (SLLA414) — return path, vias and decoupling.
- STMicroelectronics, USBLC6-2 datasheet — ESD part used in the placement example.
Reviewing a USB layout?
Send the stackup, pair length and ESD placement. We will check the impedance and return path before the board is fabricated.
