CH340 USB-UART Guide: Pinout, Clocks and Logic Levels

Real WCH CH340G chip on a NodeMCU circuit board with its original marking visible beneath the Chip-seek USB-UART guide title

CH340 USB-UART Guide: Pinout, Clocks and Logic Levels

A CH340 board can appear in the computer's device list and still be wired incorrectly for the microcontroller beside it. USB enumeration, UART voltage compatibility and the target's boot protocol are separate checks. Treating them as one problem leads to unnecessary driver changes, damaged inputs and substitutions that work on one prototype but fail on the next board revision.

This guide focuses on WCH's CH340G and CH340C in SOP-16. It uses the manufacturer's CH340DS1 V3D datasheet as its electrical reference, with other family members included only to explain selection boundaries. The photographs identify a real CH340G example; the diagrams are original connection explanations, not measured waveforms or a production-ready PCB design.

1. CH340G vs CH340C: the suffix changes the circuit

The most useful starting comparison is the oscillator. CH340G uses an external 12MHz crystal between XI and XO, with associated capacitors. CH340C integrates its clock generator, removing that external oscillator network. Both belong to the same USB-to-serial family, but the shared package outline is not permission to exchange them on an unchanged footprint and schematic.

Selected CH340 variants: package and clock differences
Part Package in V3D Clock Important selection difference
CH340G SOP-16 External 12MHz Pin 7 XI; pin 8 XO
CH340C SOP-16 Internal Pin 7 NC; pin 8 OUT#
CH340B SOP-16 Internal Configuration EEPROM; pin 7 RST#; pin 8 NC
CH340N SOP-8 Internal Different pin map and fewer exposed signals
CH340E / CH340X MSOP-10 Internal Different pin map; X adds documented I/O tolerance features

A G-to-C redesign therefore includes the crystal network, not just the purchasing line. Remove the G oscillator components, leave the C's NC pin unconnected, and treat OUT# according to its documented output function. Do not attach an old crystal network to an output because the package numbers happen to align.

Family names also hide lot-dependent differences. WCH documents additional I/O and pin-configuration capabilities for certain CH340C batches. Do not infer those features from an unqualified listing titled simply CH340C. For purchasing, retain the complete part identification, relevant batch information and the specific datasheet revision used to approve the circuit.

2. Read the CH340 pinout from the correct viewpoint

The following drawing is a top view of CH340G SOP-16, with pin 1 identified at the upper left. Pins count down the left side and back up the right. A bottom-view footprint or a rotated breakout board can look convincing while reversing the connection order, so match the actual pin-1 indicator to the PCB assembly drawing.

CH340G SOP-16 top-view pinout with pins 1 to 16 and explicit CH340C differences at pins 7 and 8
Original drawing from WCH CH340DS1 V3D, sections 3 and 4. The G pin map is shown; C pin 7 is NC and pin 8 is OUT#. Package proportions are illustrative.

For a basic three-wire UART connection, TXD is pin 2, RXD is pin 3 and GND is pin 1. The USB pair is separate: UD+ is pin 5 and UD- is pin 6. VCC is pin 16, while V3 is pin 4 and must be connected according to the chosen supply mode.

The remaining signals are not interchangeable spare GPIO. DTR# and RTS# are outputs, while CTS#, DSR#, RI# and DCD# are modem-status inputs. The hash sign denotes active-low signaling. Software can change control-line states when a serial port is opened, which matters if a board connects those lines to reset or boot circuitry.

Pin 15 on G and C is R232, an auxiliary mode input. Raising it changes RXD polarity as documented by WCH; it does not turn the pin into a high-voltage RS-232 receiver. For an ordinary non-inverted UART, retain the normal low-mode configuration rather than using R232 as a voltage-level shortcut.

3. VCC and V3: choose one documented power mode

The common V3 mistake is treating it as a freely configurable I/O-voltage pin. In the documented 5V connection, VCC receives the supply and V3 receives a 0.1uF capacitor to ground. In the documented 3.3V connection, V3 and VCC are joined and powered together from regulated 3.3V. These are different circuit arrangements.

Two CH340 power connection sketches showing 5V on VCC with a V3 capacitor and regulated 3.3V joining VCC to V3
Supply-node sketches based on WCH sections 4, 5.1 and 7.1. Both modes require local supply decoupling. The 3.3V source must be a suitable external regulated rail.
Power connections and the limits actually being compared
Mode VCC connection V3 connection V3D supply range
Nominal 5V External supply 0.1uF to ground; not tied to 5V 4.0-5.3V
Nominal 3.3V, G Regulated rail Tied to VCC 2.9-3.6V
Nominal 3.3V, C Regulated rail Tied to VCC 3.1-3.6V

Those supply ranges come from the electrical-parameter tables, whose stated test conditions include 25 degrees C. They are not a substitute for the complete temperature, timing and reliability requirements of the application. The absolute-maximum VCC figure is a stress boundary, not an alternative normal operating voltage.

Place the VCC decoupling capacitor near the package and keep its return path short. Apply the same discipline to the V3 capacitor in the 5V arrangement. Do not budget V3 as a general-purpose power output for a microcontroller, display or sensor board; this guide makes no external-load capability claim for that node.

Independent target power needs separate attention. A powered UART output can feed an unpowered device through its input structures. Check both power-up orders, disconnection and standby behavior, and use an interface with appropriate power-off protection where required. A series resistor alone does not establish safe operation for every unpowered-input condition.

4. The 12MHz crystal belongs to CH340G, not CH340C

On CH340G, XI and XO connect to the crystal network. WCH's application example uses a 12MHz quartz crystal and 33pF capacitors, while also directing designers to the crystal manufacturer's recommendations for other resonators. These example values should not replace the selected crystal's load specification or the PCB's stray-capacitance assessment.

CH340G external 12MHz crystal and capacitor network compared with CH340C internal clock and its NC and OUT pins
The G sketch follows WCH sections 5.1 and 7.1; capacitor values require the actual crystal specification. The C sketch deliberately leaves pin 7 open and adds no oscillator to pin 8.

Keep the oscillator loop compact and away from noisy switching nodes. A probe can load the circuit, so a questionable waveform taken with a long ground lead is not conclusive evidence that the oscillator is defective. Check component population, soldering and the manufacturer's clock requirements before replacing a driver that has not yet had a chance to communicate.

CH340C removes the external crystal assembly and its layout burden, but an internal oscillator is not a promise of unlimited baud-rate accuracy. Review its specified timing conditions against the target UART's error budget. A successful room-temperature terminal session is useful evidence, but it is not qualification across the final product's supply and temperature range.

5. UART wiring: cross the data paths and verify the voltage

For an ordinary full-duplex logic-level UART, connect bridge TXD to target RX, target TX to bridge RXD and the grounds together. This is a non-isolated interface; a common ground is part of the signal path. Connecting TX to TX creates two outputs on the same wire rather than a useful transmit channel.

CH340 and a 3.3V target wired with crossed TX and RX, a common ground and separate checks for power and voltage compatibility
Illustrative same-domain 3.3V UART connection, not a complete USB circuit. Both directions and every connected control line require voltage and power-sequencing checks.

Check the module schematic instead of relying on a header marked 3V3/5V. A jumper might select only the voltage exported on a power pin, leaving the bridge itself powered from USB at 5V. Measure the idle TXD voltage and verify the circuit, but use datasheet limits, not a single nominal measurement, to approve the interface.

WCH's 5V table specifies a high-level output minimum of VCC minus 0.6V under its stated output-current condition. That is already 4.4V at nominal 5V VCC; it is a guaranteed minimum, not an upper clamp for a 3.3V target. A target input must explicitly tolerate the resulting interface, or the design needs an appropriate level translator.

In the other direction, compare the target's guaranteed output high and low against CH340 input thresholds at the chosen supply. Then check absolute input limits, rise times and power-off behavior. A favorable high-level threshold comparison does not automatically establish protection against back-powering or overshoot.

Do not connect a DE-9 RS-232 port directly to these UART pins. An RS-232 application needs a line driver/receiver, as explained in the MAX3232 RS-232 transceiver guide. An RS-485 bus similarly needs a suitable differential transceiver and direction-control design; changing a terminal setting cannot supply the missing physical layer.

6. Baud rate is not useful data throughput

The CH340 datasheet describes a full-speed USB interface and UART baud-rate support up to 2Mbps. The USB link speed and the serial bit rate describe different links. Neither figure means that an application can move that many payload bytes each second continuously.

For an illustrative 8N1 serial frame, one start bit, eight data bits and one stop bit consume ten bit periods per payload byte. The ideal one-direction payload ceiling is therefore baud rate divided by ten, before USB scheduling, software delays, protocol overhead or pauses from the receiving device.

Calculated ideal 8N1 payload ceilings for four UART baud rates, explicitly excluding scheduling and protocol overhead
Calculated framing ceilings, not CH340 benchmark results or guaranteed sustained rates. At 115200 baud, 11520 payload bytes per second is the ideal 8N1 ceiling before other overhead.

At 115200 baud, a single ten-bit frame lasts approximately 86.8 microseconds. A 1000-byte transfer consequently needs at least 86.8 milliseconds on the UART wire in this simplified model. A request-response exchange will take longer if it adds a reply delay, headers, checksums or a second transfer in the opposite direction.

WCH's current USB-to-UART selection table distinguishes maximum peak baud rate from continuous-rate figures for this family. Treat the 2Mbps endpoint as a supported setting to validate, not a sustained-throughput contract. Test the actual driver, host load, target buffer and protocol together before committing to a production transfer-time requirement.

Exposed RTS#/CTS# pins also do not establish autonomous hardware flow control for every CH340 variant or driver configuration. Confirm what the selected bridge and host software actually implement. If the receiver cannot accept an uninterrupted stream, provide protocol-level pacing or select an interface whose documented flow-control behavior meets the requirement.

7. Troubleshoot the stage that actually failed

Start by classifying the symptom. No USB device, no usable serial port, garbled bytes and failed bootloader entry are different observations. Record what the host sees before changing software, then change one variable at a time so a recovered connection has an identifiable cause.

CH340 troubleshooting by observed behavior
Observation First checks What it does not prove
No USB device appears Data-capable cable, connector, VCC/V3, D+/D-, G clock That the UART baud setting is wrong
USB device appears; no usable port Hardware IDs, driver binding, OS compatibility and permissions That target RX/TX wiring is correct
Port opens; no reply Crossed data paths, common ground, target power, protocol, control lines That reinstalling USB software will help
Garbled or intermittent data Baud, framing, polarity, logic levels, noise and receiver overrun That the chip is counterfeit
Loopback works; programming fails Target boot mode, reset sequence, protocol and tool configuration That a plain UART bridge implements the programming protocol

For driver work, start at WCH's official Windows CH340/CH341 VCP driver page, or the matching operating-system link from the manufacturer product page. Check the device's identifiers and the installed driver before adding another package. The presence or absence of a preinstalled driver depends on the particular OS and installation; this guide does not prescribe downgrading to a historical version.

A useful isolation test is local loopback: disconnect the target and, on a correctly powered logic-level adapter, connect its TXD to RXD. Disable terminal local echo so it cannot imitate received data. Send a known pattern with a defined baud rate and framing, and check the returned bytes; this verifies the local path without claiming that the target protocol works.

After a successful loopback, reconnect the target and examine reset and boot-mode wiring. DTR# or RTS# may toggle when software opens the port. A programming circuit that depends on those transitions must match the specific target's documented sequence; the same pair of signals is not a universal automatic-programming interface.

8. A replacement checklist for the BOM and the bench

Start a sourcing request with the exact WCH suffix rather than the generic phrase USB serial chip. The WCH CH340G component search and WCH CH340C component search are separate starting points; the order still needs package, lot requirements and an approved manufacturer part number. Search results do not establish present stock or a qualified replacement.

  1. Map every pad. Compare the exact package drawing, pin functions and pin-1 orientation. A CH340N or CH340E is not a smaller drop-in SOP-16 substitute.
  2. Review power and clocks. Confirm VCC, V3, decoupling, crystal population and the target's I/O domain. Check power-on and power-off sequences.
  3. Check software identity. Confirm driver support, expected USB identity and any serial-number requirement. CH340B configuration capability is not a feature to assume on G or C.
  4. Exercise the real protocol. Test port opening, reset lines, sustained traffic, unplug/replug and recovery from interrupted transfers under the intended operating conditions.
  5. Retain acceptance evidence. Save the approved schematic, datasheet revision, test conditions and device identification with the BOM change.

Visual inspection helps identify package and marking mismatches, but a readable logo is not proof of authenticity. Traceable purchasing records and an application-specific receiving test are more useful than an image-only judgment. Do not convert a driver fault or a failed crystal circuit into an unsupported counterfeit allegation.

For a quotation or replacement review, send the exact part, quantity, package, target voltage, required control signals and the change being considered through the Chip-seek BOM and RFQ form. State whether the request is for the existing approved part or a redesign candidate; those are different engineering and purchasing decisions.

9. FAQ

Does CH340C need a crystal?

No. CH340C has an internal clock generator. CH340G requires the external 12MHz clock arrangement. On C, pin 7 is NC and pin 8 is OUT#, so leaving a G crystal network populated is not the documented C connection.

Can CH340 run from 3.3V?

Yes, using the documented connection that joins V3 to VCC and supplies regulated 3.3V. Check the exact suffix's supply range, every connected signal and power sequencing. Do not put USB 5V onto that joined node.

Does a 3.3V module jumper guarantee safe UART levels?

No. It may select only a header power output. Inspect the adapter schematic and bridge supply, then compare signal limits in both directions. A header label alone is insufficient evidence for a 3.3V-only target.

Is CH340 an RS-232 converter?

It is a USB bridge with logic-level serial signals. A complete RS-232 interface adds a suitable line transceiver. R232 changes an auxiliary receive-polarity behavior; it does not provide RS-232 voltage conversion.

Why is the COM port visible but the target silent?

Enumeration verifies part of the host-to-bridge path. The target can still have crossed or missing connections, incompatible voltage, the wrong baud or framing, no common ground, or an unmet boot condition. Separate those checks from driver installation.

Can CH340G be replaced directly with CH340C?

Not as an unconditional drop-in. Their SOP-16 outlines match, but oscillator-related pins differ. Review the crystal components, NC and OUT# connections, timing requirements and relevant lot-dependent features before approving a revised assembly.

10. Sources and image credit

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Turn this insight into a sourcing decision.

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