1. What is actually inside the SN74HC74?

The device contains two identical circuits, and each one is a complete D-type flip-flop: a data input, a clock input, two asynchronous control inputs, and a complementary output pair. Data present on D is captured on the rising edge of CLK. Between edges the outputs hold whatever was captured last. That single sentence is the whole function, and the datasheet's own application list is deliberately modest: turning a momentary push button into a toggle, and dividing a clock by two or by four.

The two asynchronous inputs are what separate this part from a plain register bit. Driving PRE low forces Q high; driving CLR low forces Q low, after the respective propagation delay. Neither waits for a clock edge, and both override D.

That is useful for a defined power-up state, for a hardware reset that cannot wait for a clock, and for gating a signal path. It is also the source of the most common layout mistake: a control input left floating, or firmware that assumes clear only takes effect on the next clock.

The electrical limits explain why the part is common in 5 V designs and rare as a driver. Recommended operation is 2 V to 6 V, absolute maximum supply is 7 V, and each output is specified for ±4 mA at 4.5 V. Continuous output current is rated at ±25 mA as an absolute maximum, a stress limit rather than a design target. An LED, a relay coil or a long cable belongs behind a transistor, not on Q.

2. Which pin does what on the 14-pin package?

Pin 1 is marked by the notch or the dot, and the numbering runs counter-clockwise when the package is viewed from above. The arrangement is not symmetric: channel 1 occupies pins 1 to 6 with its outputs at 5 and 6, while channel 2 puts its inverted output at pin 8 and its true output at pin 9. A schematic symbol that draws the two halves identically will still be correct logically, but a footprint drawn from that symbol without checking the pin table will swap Q and Q-bar on the second channel.

Every unused input needs a defined level. An open CMOS input can drift into the transition region, increasing supply current or allowing unintended switching. For an unused channel, hold PRE and CLR high and tie D and CLK to defined static levels; do not tie both asynchronous controls low. The same review applies when only half the package is used in a divider circuit.

3. How do preset, clear and clock interact?

The function table is short, and its ordering matters more than its length. Preset and clear are evaluated first. Only when both are inactive does the clock have any authority, and only a rising edge counts. A high level held on CLK does nothing; a low level held on CLK does nothing.

Two details in that table are easy to miss. First, both controls low produce Q and Q-bar high at the same time. The datasheet calls this configuration nonstable, meaning it does not persist once either control returns high, and the outputs are no longer complementary while it lasts. A design that can assert preset and clear together should be treated as a logic error rather than a defined state.

Second, there is a setup requirement on the controls themselves. Before the next clock edge, preset and clear must have been inactive for at least 5 ns at 4.5 V, rising to 6 ns over the full temperature range. This prevents a race in which the clock captures a level while a control is still returning high. Firmware that clears the flip-flop from a GPIO and then immediately clocks data can violate this if the two actions are close in time, and the failure appears as an occasional lost or duplicated event rather than a clean error.

To turn a momentary contact into a toggle, feed Q-bar back to D. Each press produces one clock edge and the output changes state once. Contact bounce produces many edges, so the input still needs debouncing, either in hardware with an RC network and a Schmitt-trigger buffer, or in firmware. To divide a clock by two, tie D to Q-bar and use Q as the divided output; the second channel can then divide the same clock by four if it is clocked from the first channel's Q.

4. Which timing numbers decide whether a design works?

At 4.5 V, data setup time is 20 ns at 25 °C and 25 ns over −40 °C to 85 °C. The specified hold requirement is 0 ns at the input pins under the stated conditions. This does not remove the setup requirement or make asynchronous data safe: skew, jitter and metastability still need a system-level review.

Clock high and low pulse widths are 16 ns at 25 °C and 20 ns over temperature. Preset or clear low pulse width is 20 ns at 25 °C and 25 ns over temperature.

Check frequency, pulse width and propagation delay separately. At 4.5 V, fmax is specified at a minimum of 31 MHz at 25 °C and 25 MHz over −40 °C to 85 °C; its typical value is 50 MHz. At 6 V the corresponding minimum values are 36 MHz and 29 MHz. These numbers describe the maximum operating clock capability, not a required minimum clock speed.

For the TI switching table's test conditions, clock-to-output delay at 4.5 V is 20 ns typical, 35 ns maximum at 25 °C and 44 ns maximum over temperature. Preset/clear-to-output delay is also 20 ns typical, with 46 ns and 58 ns respective maxima. Use the applicable maximum for a downstream timing budget, and independently meet the minimum control pulse width; propagation delay is not the minimum permitted pulse width.

One specification is often ignored because it does not look like timing at all: the input transition rise and fall rate. The recommended maximum is 500 ns at 4.5 V, tightening to 400 ns at 6 V, and it exists because slow edges leave the input sitting between thresholds, where a CMOS input draws current and can oscillate. A push button with a large series resistor, or a signal arriving through a long RC filter, is exactly the case the datasheet warns about. Buffer it with a Schmitt-trigger device before the clock or control pin.

5. Can a 3.3 V controller drive a 5 V flip-flop?

It depends on which version is on the board and which direction the signal travels. The HC version uses standard CMOS thresholds, and the datasheet states them at three supply voltages only. At 4.5 V, a valid high input is at least 3.15 V and a valid low is at most 1.35 V. At 6 V the limits are 4.2 V and 1.8 V; at 2 V they are 1.5 V and 0.5 V.

Calculate margin from the driver's guaranteed VOH(min) and VOL(max), not its supply label. At the tabulated 4.5 V receiver condition, an assumed driver VOH(min) of 2.9 V gives a high-level margin of −0.25 V for HC and +0.9 V for HCT. This is a calculated example, not a measured driver specification; a nominal 3.3 V rail alone proves neither result.

The reverse direction is the trap. An HCT output swings to its own VCC, so on a 5 V rail it produces a 5 V high level. Feeding that directly into a 3.3 V microcontroller pin is outside that pin's absolute maximum in most families. Accepting a 3.3 V input on a 5 V part and driving a 3.3 V input from a 5 V part are two different problems, and only the first is solved by choosing HCT.

A 3.3 V supply sits between the tabulated 2 V and 4.5 V points. The datasheet does not publish a threshold for it, so do not interpolate and assume. Either confirm with the vendor, or run the part at 4.5 V and shift levels, or select a device specified for the rail in use. The recommended operating range does allow 3.3 V operation electrically; the question is only whether the guaranteed input levels are comfortable for the source driving them.

6. Which package should the footprint use?

Five surface-mount and through-hole body sizes are offered for the commercial part, plus ceramic packages for the extended temperature devices. They share a pinout but not a footprint, and two of them look similar in a schematic without being interchangeable on a board.

Thermal behaviour differs by package: the cited junction-to-ambient figures are 61.9 °C/W for PDIP, 133.6 °C/W for SOIC and 151.7 °C/W for TSSOP under TI's test conditions. Check total dissipation, board conditions and output-voltage guarantees; the ±25 mA stress rating is not an operating target. The military 20-pin LCCC also has unconnected pins and different numbering, so it cannot use a 14-pin land pattern.

7. Which alternatives are drop-in? Key differences and compatibility

Three families show up most often in cross-reference requests, and only one of them is a same-footprint swap. The table below separates logic compatibility from physical compatibility, because confusing the two is how a "second source" turns into a respin.

SN74HCT74 is a same-pinout candidate at a 5 V rail, subject to qualification. Match the actual orderable package and drawing; then compare setup, hold, control recovery, propagation delay, load and supply-current conditions. A shared logical function does not establish identical timing or power behavior.

HCT is specified only from 4.5 V to 5.5 V, so it does not replace HC in a 3.3 V or 2 V design. TTL-compatible thresholds simplify an upward interface, but both high and low margins still require guaranteed driver values. Also check HCT input-stage current at the actual high input voltage and the return signal's voltage limits.

CD4013B is a functional alternative requiring a redesign. Its set/reset inputs are active high, its pin arrangement differs, and its clock capability is lower at a comparable supply. The cited TI typical clock figures are 7 MHz at 5 V, 16 MHz at 10 V and 24 MHz at 15 V; they are not guaranteed minima. Compare the full temperature, loading and output-voltage conditions before making an electrical equivalence claim.

CD4013B supports a 3 V to 18 V recommended supply range. That makes it relevant to a 12 V or 15 V legacy circuit where HC74 cannot operate directly. It remains a different design choice: qualify its particular supply, temperature, signal levels and load rather than treating its wider supply range as evidence of interchangeability.

Second-source HC74 devices from other manufacturers are generally sold against the same 74-series pin arrangement, but "generally" is not a release criterion. Confirm the pinout and the package drawing on the specific vendor datasheet before releasing a footprint, and confirm the temperature grade, because the commercial and extended parts share a pinout but not a specification.

8. What must be verified before substituting? A migration checklist

A substitution is safe when six items have been checked against the actual datasheet, not against a distributor's cross-reference field.

1. Pinout and control polarity. Confirm that PRE and CLR are active low on the candidate, and that Q and Q-bar land on the same pins. The CD4013B fails both tests.
2. Supply range versus the rail in use. A 3.3 V rail rules out HCT. A 12 V rail rules out the entire HC family.
3. Input thresholds at the real supply. Compare the driving device's guaranteed VOH and VOL against the receiving part's VIH and VIL at the same rail, with temperature included.
4. Clock frequency and pulse width. Use the guaranteed minimum maximum frequency, not the typical number, and check that the clock source's minimum high and low times exceed the specification.
5. Setup and hold around the clock edge. At 4.5 V over the cited temperature range, meet 25 ns data setup and 6 ns preset/clear recovery before the active edge. Check hold, board skew and clock jitter separately.
6. Output drive and load. Verify the load current against the specified drive at the chosen supply, and keep absolute maximum currents out of the design margin.

For a same-pinout second source, document all six checks even when the footprint remains unchanged. For CD4013B, expect schematic, control-polarity and timing changes. Record the exact approved manufacturer and suffix so purchasing cannot turn a qualified part into an unrestricted family-level substitution.

9. How do you avoid counterfeits when the price drops?

An unexpectedly low quotation is a reason to investigate the lot and commercial terms, not proof of counterfeiting. Use a documented inspection plan with three complementary checks:

• Marking and packing. Compare the top marking, the pin-one indent, the lead finish and the reel or tube label against the manufacturer's marking specification. Re-marked parts often differ in laser depth, font weight or the country-of-origin line.
• Electrical screening. Check function, timing and output levels under controlled conditions. VI signatures can help compare samples with a validated reference, but cannot by themselves authenticate a die or replace functional qualification.
• Traceability. Request the lot, date code, packaging labels and available purchase-chain records. Escalate missing evidence under the project's acceptance procedure rather than treating a working sample as proof for the whole lot.

Risk-based X-ray or specialist inspection can reveal construction differences, but legitimate manufacturing changes also exist. Compare against an appropriate validated reference and resolve anomalies with the manufacturer or qualified laboratory. No single visual, electrical or X-ray result proves authenticity.

10. What belongs in the sourcing request?

When this part is short, a request that names the constraints gets a usable answer; a part number alone does not. A supplier can confirm stock against a specific orderable code, but cannot guess whether an HCT device will do. Ask with the full code, the package suffix, the temperature grade and the logic family the design depends on.

Useful fields are the orderable part number and package suffix, the quantity per build with annual volume, the supply rail and driving logic family, whether an HCT device is acceptable, the clock frequency the circuit runs at, and whether the date code or manufacturer marking matters for the customer's approval. Where the design was qualified against one vendor, say so: a different vendor's die is a different qualification even with an identical datasheet.

For current availability on this family, search the SN74HC74 listing and the 74HCT74 listing on chip-seek.com. Both pages return live catalogue results rather than a stock claim; confirm quantity and date code against the quotation. If the BOM contains several logic families, the component availability guide explains how lead times are reported, and a multi-line request can be submitted through the BOM and RFQ form.

Frequently asked questions

Is the SN74HC74 the same as a 74HC74? Functionally yes. "SN" is the manufacturer prefix and the digits after it identify the family, so a 74HC74 from another vendor should behave the same way. The prefix, package suffix and temperature grade are what distinguish orderable parts, and those are the fields to compare.

Can I substitute an SN74HCT74 for an SN74HC74? It is a candidate at 5 V, subject to package and electrical qualification. The pinout matches, but supply range, input current and timing conditions must be checked; HCT is not suitable for a 3.3 V supply.

Can I replace it with a CD4013B? A redesign is required. Its pinout, active-high set/reset controls, clock specifications and output drive differ. Its 3 V to 18 V operating range makes it an option to qualify for higher-voltage circuits, subject to the complete electrical requirements.

What happens if preset and clear are both asserted? Both Q and Q-bar go high. The datasheet describes this as nonstable, meaning the state disappears when either input returns high, so it should be treated as an invalid condition rather than a usable state.

Do unused inputs need resistors? They need a defined level. Tying them to VCC or GND is normal. A resistor is only needed when a signal can be disconnected or driven by a source that goes high impedance, and then it must be sized so the input still reaches a valid level.

How fast can it clock? At 4.5 V, 31 MHz at 25 °C and 25 MHz over −40 °C to 85 °C, both guaranteed minima. At 6 V the guaranteed figure is 36 MHz at room temperature. Typical devices run faster, but the guaranteed column is the design number.

How much current can an output sink? The datasheet specifies ±4 mA at 4.5 V with the corresponding output voltage limits, and the absolute maximum continuous output current is ±25 mA. The second number is a survival limit, not a design target.

Why does the part get warm in a slow-input design? Because the input spends time between the thresholds, where a CMOS input conducts. The transition rate limit of 500 ns at 4.5 V exists to prevent this. Add a Schmitt-trigger buffer ahead of the slow signal.

Sources

• Cover photograph: Raimond Spekking, STMicroelectronics 74HC00 on a controller board, CC BY-SA 4.0. Chip-seek cropped and arranged the cover under the same licence. The photo illustrates the HC family; it is not an SN74HC74, an authenticity reference or inventory evidence.
• TI SN74HC74 / SN54HC74 datasheet, SCLS094F, revised June 2021: pin configuration, function table, recommended operating conditions, timing requirements and switching characteristics.
• TI SN74HCT74 / SN54HCT74 datasheet, SCLS169G, revised October 2022: pin configuration, supply range and TTL-compatible input thresholds.
• TI CD4013B datasheet, SCHS023E, revised September 2016: pin functions, active-high set and reset behaviour, supply range, clock frequency and output current.
• TI SN74HC74 product page for current package and orderable options.

Need a verified second source?

Prefer to check the family first? The 74HCT74 listing covers the TTL-compatible version of the same pinout.