USB-C and SuperSpeed: A Practical Introduction
USB-C is not a speed. It is a 24-pin connector with two roles, a power negotiation protocol, and — optionally — two extra high-speed pairs. Mixing those up is the usual first mistake.
Quick Answer
- Connector: 24 pins in two mirrored rows; the cable works either way up.
- Roles: CC pins and a 5.1 kΩ pull-down (sink) or a pull-up (source) decide who powers whom.
- Power: 5 V by default; USB PD raises it to 20 V / 5 A (100 W), and EPR to 48 V / 5 A (240 W).
- Speed: SuperSpeed pairs are separate from D+/D−; 85 Ω differential, 100 nF AC coupling on TX.
1. The connector
The 24 pins fall into four groups: power (VBUS/GND), USB 2.0 (D+/D−), configuration (CC1/CC2), and SuperSpeed (TX/RX pairs, plus SBU for alternate modes). The mirroring means the host has to handle either orientation — usually with a CC-based mux, or by wiring both rows together where the standard allows.
Two practical consequences of the mirroring. First, USB 2.0 D+/D− can usually be tied together across the two rows, because only one pair is active at a time and the protocol tolerates the stub. Second, SuperSpeed cannot be tied: the TX and RX pairs swap when the plug is flipped, so a mux (or a controller with integrated orientation detection) is required for full-speed operation.
If the product only uses USB 2.0 over a USB-C connector, that mux is unnecessary — one of the few places where a simpler design is also correct.
| Pins | Function | Notes |
|---|---|---|
| A4, A9, B4, B9 | VBUS | Four pins, up to 5 A with an e-marked cable |
| A1, A12, B1, B12 | GND | Return and shield reference |
| A5, B5 | CC1, CC2 | Role detection and PD communication |
| A6, A7, B6, B7 | D+, D− | USB 2.0, 90 Ω pair |
| A2/A3, A10/A11, B2/B3, B10/B11 | SSTX / SSRX | SuperSpeed, 85 Ω pairs |
| A8, B8 | SBU1, SBU2 | Alternate modes (DisplayPort, audio) |
2. CC pins decide the roles
Sink (device): CCx -- 5.1 kOhm -- GND Source (charger): CCx -- Rp -- VBUS Rp 56 kOhm: default current Rp 22 kOhm: 1.5 A Rp 10 kOhm: 3 A
If your board has a USB-C receptacle for power and the CC pins are left floating, a C-to-C cable will not deliver power at all. The device looks dead, and the charger sees nothing. This is the single most common USB-C design error, and it costs two resistors to fix.
For a device that both charges and acts as a host, the CC network is more complex: the port has to switch between Rd and Rp, and a PD controller handles the negotiation. At that point, read the controller datasheet rather than copying a reference schematic.
PD negotiation runs over the CC line as a modulated signal, not as a static resistor. The source advertises capabilities, the sink requests a profile, and both sides acknowledge before the voltage changes. If you are debugging "it charges slowly", look at the negotiated contract, not only at the resistors.
3. Power negotiation
| Mode | Voltage / current | Power |
|---|---|---|
| Default USB | 5 V / up to 3 A | 15 W |
| USB PD | 5–20 V / up to 5 A | up to 100 W |
| PD EPR | 28–48 V / up to 5 A | up to 240 W |
Above 3 A, the cable must be electronically marked, and the sink should not assume the full current is available until the negotiation completes. A design that hard-wires a 5 A load to VBUS will either brown out or trip protection.
4. SuperSpeed signaling
SuperSpeed adds one transmit pair and one receive pair in each direction. They are AC-coupled: 100 nF in series on each line, placed near the transmitter. They are also faster and less forgiving than USB 2.0 — Gen 1 is 5 Gb/s, Gen 2 is 10 Gb/s, and USB4 goes higher.
Practical routing rules: keep the pairs short, match within the pair, avoid vias, and do not route them under the connector where the return path is broken. If the design only needs USB 2.0 over USB-C, the SuperSpeed pins can be left unconnected — but they still need ESD protection if they are exposed on the receptacle.
Because the connector is reversible, the SS lanes must be swapped by the mux when the plug is flipped. That means the PCB sees two possible mappings, and the mux adds its own capacitance and loss in the path. At Gen 2, that is part of the link budget, not an afterthought.
Signal conditioning is built into many USB 3 controllers: transmitter de-emphasis and receiver equalisation compensate for the loss of the PCB and the cable. That is why a link can work at Gen 1 and fail at Gen 2 on the same board — the extra loss at 5 GHz exceeds what the equaliser can recover.
| Rule | Why |
|---|---|
| 85 Ω differential for SS pairs | Different target from the 90 Ω D+/D− pair |
| 100 nF AC coupling on TX | Required by the specification; one per line |
| No vias if avoidable | 5–10 Gb/s is far less tolerant than USB 2.0 |
| Continuous return under the pairs | The connector area is where planes get cut |
| ESD on CC, SBU, VBUS, D+/D− | Every exposed pin can be touched |
5. Common mistakes
| Mistake | Symptom | Fix |
|---|---|---|
| No CC pull-down | C-to-C cable gives no power | 5.1 kΩ on both CC pins |
| CC resistors on one pin only | Works one orientation, fails the other | One per CC pin (or a mux) |
| AC caps on RX side | Link training fails | Move to the TX side |
| 90 Ω routing for SS | Marginal eye, intermittent link | 85 Ω per stackup |
| No ESD on CC/SBU | PD controller dies on a zap | Protect every exposed pin |
5b. Power path and protection
A USB-C port can be asked to deliver 100 W or to receive it, and the VBUS pin is exposed to the world. Three things follow: protection on VBUS, a power path that can handle the negotiated current, and a plan for what happens when the source is a 5 V phone charger rather than a 20 V supply.
- ESD: VBUS, CC, SBU and the data pairs all need protection at the connector.
- Inrush: a large input capacitor looks like a short when the cable is plugged; use a soft-start or an eFuse.
- Reverse voltage: if the port can be both source and sink, the power path has to block in both directions.
- Current: 5 A through a connector and a small board requires wide copper and a thermal check.
6. Bring-up checklist
- Check CC voltage with a C-to-C cable: a sink should see the source's Rp and pull the line to a defined level.
- Verify 5 V on VBUS in both plug orientations.
- If PD is used, capture the CC waveform and confirm the BMC negotiation; check the requested voltage.
- For SuperSpeed, run a link test and read the negotiated speed; enumerate at Gen 1 and Gen 2 separately.
- Probe the SS pairs only with a differential probe or a compliance fixture; a single-ended probe on one line destroys the measurement.
- Check ESD on every exposed pin, including SBU.
- Thermal: run at maximum negotiated power for 30 minutes and measure the connector and the PD controller.
For the differential-pair fundamentals that also apply here, see the guide to USB 2.0 differential pair routing, and for the protection placement on the same connector, the ESD layout guide.
7. FAQ
Is USB-C the same as USB 3?
No. USB-C is a connector; USB 3 is a speed. A USB-C port can carry only USB 2.0, and a USB-A port can carry USB 3.
Why does my device not charge from a C-to-C cable?
Almost always the CC pins. A sink needs 5.1 kΩ from each CC pin to ground; without it the charger sees no device.
Can I get 100 W from any USB-C port?
No. The source, the cable (e-marked) and the sink must all support PD and the requested voltage. Default USB-C is 5 V.
Do I need a PD controller?
Only if you need more than 5 V or more than 3 A, or if the port must switch roles. For a simple 5 V device, two resistors and a protection array are enough.
Why does my board work with an A-to-C cable but not C-to-C?
An A-to-C cable provides 5 V regardless of the CC state. A C-to-C cable waits for the sink to present Rd. The same design that "works" with an A-to-C cable can be completely dead with C-to-C.
Are SuperSpeed pairs required?
No. If the product only needs USB 2.0, the SS pins can be left unconnected — but they must still be protected if exposed.
Can I test USB-C without a PD analyser?
Partly. A meter on VBUS and CC tells you the role and the default voltage; full PD negotiation needs a PD-aware tester or a protocol analyser. For most bring-up, the simpler check catches the common faults.
What is an e-marker?
A small chip in the cable that tells the source its current and data capability. Without one, the source limits current to 3 A.
8. Sources
- USB Implementers Forum, USB Type-C and USB 3.2 specifications — pinout, CC, PD and SuperSpeed requirements.
- USB-IF, USB Power Delivery — voltage and current profiles, EPR.
- Texas Instruments, High-Speed Layout Guidelines (SLLA414) — pair routing and return path.
- Vendor USB-C controller datasheets — CC network and mux configuration.
Designing a USB-C port?
Tell us the role (sink, source or both), the power level and the data rate. We will check the CC network, the protection and the pair routing before you commit.
